JTAG Technologies has once again boosted the performance of its ProVision suite of boundary-scan development tools with the addition of 11 enhancements. The first of these is the addition of all instructions handling (including private instructions) within ProVision's JTAG Functional Test (JFT) capability, now giving users easier access to device registers [other than just those needed for IEEE Std. 1149.1boundary-scan operations]. For example, registers needed to invoke on-chip emulation modes and programming registers can now be accessed using JFT's Python routines.

The second enhancement is the addition of 'netlist type autodetect', which automatically recognizes netlist formats as belonging to certain tool vendors. This can save considerable time when importing netlists from third parties. Thirdly, the WGL test vector format (as used for IC testing) is now supported through a ProVision plug-in.

The fourth enhancement is the ability to test (IEEE) 1149 dot 6 to dot 1 connections; an industry first in terms of cross-standard testing within a single tool.

The remaining seven enhancements are:

5) Support for FTDI USB to serial port peripheral devices (embedded on target board)

6) HTML reporting for TTR and BSD in AEX sequences

7) The ability to export and re-import AEX sequences

8) Support for double-latching bus logic

9) Boundary-scan register length check

10) Support for multiple ID codes in BSDL

11) 64-bit drivers for DataBlaster hardware.

The above enhancements to ProVision are all available on CD17, which also contains the recently announced ProVision Designer Station (PV_DST); support for additional microprocessors with embedded flash and a new Production Integration Package (PIP) for supporting .NET (for interfacing with Microsoft applications) has been added to the range of existing PIP packages.

Customers with current support licences for ProVision and PV_DST will receive CD17 as a matter of course.