What current power saving techniques work well in wireless networking systems today?

The topic for the July question is Power Management. Current wireless network power management can often times substantially degrade performance and may even increase overall energy usage. Representatives from ChipVision, Micrel, and ON Semiconductor offer their comments in response to the question:

Jacques Lavernhe, ON Semiconductor
During operating phases, a wireless Physical Layer (PHY) always transitions from sleep to active states. International Standards define how and when a device should wake up to enter in active state.

Besides Power Saving protocols defined in the standards, protocols implementation generates high power save gain.

In sleep state, the RF functions are off, but digital cores are still active. Dynamic voltage (DVS) and dynamic frequency (DFS) scaling can save a significant amount of power. Neglecting the DC leakage currents, the power dissipation approximation is given by: (C = capacitance switched/clock cycle, V = voltage, f = frequency).

Although this is not exact, because integrated chips do not use only CMOS, the dissipated power decreases quadratically with the voltage and linearly with the frequency. However, this method is not popular because of the latency generated to come out of sleep, but algorithms that can efficiently predict burden of the digital core may significantly improve sleep state consumption.

Coming out from sleep mode techniques can also significantly improve the overall consumption. Plot of power current versus time shows spike current when the device transitions from state to state. The longer the device takes to come in and out the active Tx or Rx state, the poorer the efficiency.

Because scaling data rate up and low does not significantly change average power consumption, higher data rate can also save power. Compared to 1 Mb/s Bluetooth, a 100 Mb/s UWB 4GB transfer consumes about 10 times less power.
Hardware design is also key factor in the power optimization techniques. Compared to a costly discrete implementation, an integrated Power Management IC offers much more power state granularity to the hardware and then much more efficiency in the power usage.

Andy Cowell, Micrel, Inc.
The power saving techniques that work well in wireless networking systems today are three fold: judicious power and system management through the active enabling and disabling of circuit blocks when not in use; the correct choice of power management components using highly efficient DC/DC converters whenever possible; and finally, using low noise, high efficiency step-down DC/DC converters in the RF section, i.e. in 3G datacards or in WLAN, to power the power amplifiers.

The first technique, on-off switching of circuit blocks speaks to the current trend of “green” power management where state-of-the-art load switches, such as those offered by Micrel, enable the system designer to completely disconnect circuit blocks from the power source to reduce energy consumption when that block is not needed.  The ability to meticulously manage when and how blocks of power consuming components are turned off and on will result in significant power savings across multiple segments of any given wireless network.

The second technique, power distribution involves using highly efficient DC/DC converter technology to save power even when the load is in power save mode. The patented architecture implemented in Micrel’s MIC23031, for example, delivers >85% efficiency at 1 mA output load with state-of-the-art low noise, transient performance.

The final technique involves taking low noise DC/DC converter technology and applying it directly to the RF power amplifier stage that some wireless networking technologies can use. In linear RF systems, power usage is inversely proportional to signal strength so the stronger the RF signal, the less power that is required and the DC/DC converter allows the system to save that energy instead of simply burning that power in the power amplifier.

Dr. Lars Kruse, Chief Architect, ChipVision Design Systems, Inc
Wireless networking standards define several power-saving protocols such as Unscheduled Automatic Power Save Delivery (u-APSD) and Power Save Multi-Poll (PSMP) (part of the 802.11 standards) to give wireless devices idle time during which chip-level power-saving modes can be activated. These power-saving modes avoid wasted computations, thus minimizing dynamic power consumption, and reduce leakage power consumption. In general, the longer the device idle periods, the more aggressive the power-saving modes that can be applied. If minimizing energy consumption to maximize battery lifetime is the design intent, increasing power consumption for short periods of time – to transmit bursts of data packets, for example – achieves longer idle time after the data transmission.

System-level simulation analysis tools like ChipVision’s P-SAM can be applied to find a good trade-off between active and idle times. Chip-level power-saving modes with data and clock gating reduce dynamic power. They avoid glitches in the data path and unnecessary toggling in the clock tree. These techniques applied during chip design add minimal overhead in performance or chip area. You can read Dr. Kruse's complete comment at

Another way to save power is to run chip-level blocks at the lowest possible voltage. Dr. Kruse's complete comment is posted on