Phase-locked loop simulation continues to be a big challenge for designers. The combination of RF and digital circuits makes PLL simulation at the transistor level particularly difficult.

By Andy Howard, Agilent EEsof

Phase-locked loop design and simulation continue to present major challenges for wireless system and RFIC designers. PLLs must be designed to meet requirements and specifications such as tuning range, tuning resolution, closed-loop phase noise, stability, spurious signal suppression, modulation response, transient response time,

click to enlarge

Figure 1. A simple PLL block diagram with a sigma-delta modulator to generate the time varying divide ratio.
and power consumption, among other things. PLLs are difficult to simulate because they are mixed-domain circuits. PLL synthesizers have an RF or microwave voltage-controlled oscillator, a much lower frequency, very stable reference oscillator, a frequency divider that is realized from digital circuits and is programmable, a phase/frequency detector that is also implemented from digital circuits, and a low-frequency loop filter. PLL synthesizers often require a means of applying a phase or frequency modulation signal into the loop. Figure 1 shows an example PLL block diagram.

There are two main decisions to make when simulating PLLs. One is the type of simulator(s) to use, and the other is the level of abstraction at which to model the PLL. There are simulators such as Spice, harmonic balance, and Envelope that handle transistor-level models. These types of simulations should be most accurate, but may be impractical for PLLs due to time and/or memory requirements if simulating everything at the transistor level. Using a higher level of abstraction to model the PLL and its components via behavioral models can make design tasks and simulations much faster, although with some potential loss of accuracy.

It is also important to decide what you are going to simulate. It is unlikely that there will be enough time to simulate all the possible frequency transition times, and the phase noise and spurious signal levels at different frequency settings over all the different process corners, and so on.

The combination of RF and digital circuits makes PLL simulation at the transistor level very difficult. The phase frequency detector is an asynchronous digital circuit that operates on waveforms with sharp transitions. This, along with the need to accurately simulate the time differences between the input signals, necessitates use of a small simulation time step. If using a purely time-domain simulator, the VCO circuit will also require that a small simulation time step be used to adequately capture the harmonics. If simulating phase noise, you only need to wait until the circuit has reached steady state. But commonly-used time-domain simulators like Spice and its derivates may not be able to simulate noise in the time domain. If you need to simulate transient responses, such as how long it takes for the VCO to settle from one frequency to another, millions of time points may be required depending on the ratio of the settling time to the time step.

Harmonic balance does simulate noise in nonlinear circuits, but requires more and more memory as the divide ratio increases. Noise is treated as a small-signal perturbation on the large-signal solution. Because of the frequency divider, harmonic balance needs the initial guess generated from a transient simulation to successfully solve the circuit. Harmonic balance cannot be used for transient (non-steady-state) simulations.

Linear models may be used with AC circuit simulation to model and optimize a PLL’s frequency response and phase noise. This technique allows arbitrary topologies and phase noise sources to be included and is very fast. It also enables you to see which noise sources contribute the most to the total noise at the output of the PLL. Alternatively, you may use mathematical tools to simulate PLLs or algorithms.

Co-simulation with Ptolemy (a numeric and time-synchronous data flow simulator) offers the ability to model more complex PLLs such as those that use a sigma-delta modulator to set the frequency. The Ptolemy-level components enable quick modification, for example, of the order of the sigma-delta modulator, the number of bits used, and the desired fraction (when simulating a fractional-N PLL.) You may add a dithering signal into the Ptolemy simulation to see its effect on spur reduction. While Ptolemy is used to model the sigma-delta modulator that generates a time-varying divide

click to enlarge

TFigure 2. The Envelope simulator mixes frequency- and time-domain simulation, which gives more efficient and accurate simulations than a purely time-domain based simulator such as SPICE.
ratio, the PLL that utilizes this divide ratio may be simulated using Envelope. The PLL utilizes mostly behavioral models, but it may have a transistor-level phase/frequency detector, charge pump and loop filter. It is also possible to include time-domain phase noise data to simulate the VCO output spectrum including quantization noise due to the sigma delta modulator as well as phase noise from the VCO and reference oscillator. Noise may be introduced at other points in the PLL as well.
Envelope Simulator Offers Advantages
The Envelope simulator mixes frequency- and time-domain simulation capabilities. You specify analysis frequencies and the simulation time step and stop time. For a PLL, the analysis frequencies would be the nominal center frequency of the VCO and its harmonic frequencies. The inverse of the simulation time step gives the bandwidth around each analysis frequency within which signals must remain in order to be included in the simulation. The Envelope simulator enables you to see transient responses in frequency, phase and amplitude of signals within each analysis bandwidth, including the baseband envelope. A block diagram showing the mix of frequency — and time-domain simulation on the example PLL is shown in Figure 2.

When simulating transient responses, the benefit of this approach is that you can quickly simulate long (milliseconds) transient responses in a short period of time because a much larger time step may be used than would be required if simulating the entire loop using a purely baseband, time-domain simulator such as SPICE.

The Envelope simulator also performs noise simulation in the time domain. The noise is treated as part of the large-signal solution and is not handled any differently from other signals. (The Envelope simulator has the option of running a separate noise analysis after the last time point. In this case, the circuit is assumed to be in steady state after the last time point, and the noise analysis is the same as is run with harmonic balance.)

When running time-domain noise analysis or spurious analysis, it is optimal to start the simulation with the loop as close to steady state as possible. If there is a turn-on transient that you want to ignore, you may delay when the simulator starts saving data. The stop time will determine the spectral resolution of the noise simulation and the time step will determine the highest offset frequency. If you need to see a noise spectrum that includes both close-in resolution and high offset frequencies, then both a small time step and a large stop time will be required, possibly leading to a long simulation time. Also, when running noise analyses, it may be preferable to run several simulations and average the results together to get a smoother response.
Generating Behavioral Models
For at least some PLL simulations, it will be worthwhile to use behavioral models. This is because the simulations will be faster and the design will be easier to modify to seek improvements with behavioral models. How do you create behavioral models? This depends on the type of component. There are a number of built-in PLL behavioral models that are based on two equation-based behavioral modeling components in Advanced Design System the

click to enlarge

Figure 3. Results from a Ptolemy co-simulation, using a sigma-delta modulator to generate the time-varying divide ratio. The PLL’s phase/frequency detector and charge pump were modeled at the transistor level.
SDD (symbolically defined device) and FDD (frequency-domain defined device.) The SDD and FDD enable you to define nonlinear components using equations on the schematic without the need for source code. Many of the PLL behavioral models are based on these components.

It is relatively easy to generate a behavioral model for an oscillator, including phase noise. You can simulate a transistor-level VCO, sweeping the tuning voltage and calculating the phase noise using harmonic balance. The resulting phase noise data may be read from the dataset and re-used in another simulation using the Envelope simulator. Alternatively, you may just type into a text file pairs of offset frequency and phase noise data.

A phase/frequency detector and charge pump behavioral model may be created by running a transient simulation of the transistor-level circuit by itself, driven by two square-wave input signals. You sweep the phase difference between the input signals and see the mean charge pump current as a function of the phase difference. The slope of the resulting curve is the sensitivity in Amperes per degree. The behavioral model enables you to specify a deadzone time as well as different slopes depending on whether the phase difference is positive or negative.

Phase/frequency detectors and charge pumps are highly nonlinear circuits with behavior that is difficult to model. For this reason, it is valuable to be able to use the transistor-level circuit directly, when higher accuracy is needed.

A behavioral model that combines the VCO and frequency divider speeds up transient response simulations because it enables the time step to be only small enough to capture the variation in the divided signal phase and frequency, which varies at a much lower rate than the VCO. The results are shown in Figure 3.

While phase-locked loops remain a difficult simulation problem, Agilent offers a wide range of simulation and modeling capabilities, making the task easier. We offer the ability to simulate arbitrary loop topologies and post-process the results with ease and flexibility. Co-simulation between Ptolemy and Envelope enable you to investigate the effects of, for example, sigma-delta modulator topology and transistor-level phase/frequency detector non-idealities at the same time.

About the Author
Andy Howard is an applications engineer for Agilent EEsof;