By Dr. Lawrence Williams, Ansoft

Engineers designing portable electronic devices like cell phones and PDAs are driving an industry trend to integrate rich digital content with wireless connectivity and extended battery life. A modern cellular handset, for example, is hardly just a telephone. Modern systems integrate RF/Analog/Digital System on Chip (SoC) solutions with memory, graphics, storage, GSM radio, Bluetooth/802.11x radio, antenna, LCD, camera, MP3, and broadcast FM. Extreme integration creates new challenges for RF performance, system signal integrity, system-level EMI, low power, and communications reliability. A higher level of simulation is needed with greater coverage of interaction across domains, model abstraction, and hierarchy.

Explosive growth in wireless handheld devices with integration at the system level has led to even greater integration at the integrated circuit level. Digital, analog, and mixed-signal single chip solutions are driving to the 90nm CMOS process and beyond. Scaling to this process enables greater performance and significantly lower power, however, new risks impact RF, analog, and high-speed circuit design. SoC design and verification requires new levels of simulation performance and capacity, time- and frequency-domain simulation, plus sensitivity analysis to account for design for manufacturing (DFM) variations. Tight coupling between circuit simulation and parameterized electromagnetics allows engineers to examine pre-layout routing alternatives and the attendant coupling to see how they impact performance at the circuit level.

Integration is also observed at the packaging level. The emergence of stacked die, package on package (PoP) 3D packaging solutions requires a new approach to design with performance verification of the package, board, and circuit together. SiP often involves three or more separate companies: two or more chip vendors plus a package vendor. Models may come from disparate sources and/or EDA vendor file formats. An integrated, comprehensive simulation is required. Modern compute power combined with clever data management allows solution of very large packaging problems accurately and efficiently. Rapid analysis of various routing alternatives during the design phase is critical and post route verification for the full design using 3D EM simulation ensures package performance coupled to IC netlist circuit simulation.

A silicon vendor may produce a wireless SoC that performs flawlessly at the packaged part level. Once that part is placed on a system PCB, the complex interactions among traces on the board, the coupled impedances between package pins and the PCB, and nonlinear effects in the circuit itself can combine to produce anomalous behavior. Add to that fact that the system PCB also includes interfaces to graphics and memory with distinct digital switching events that can lead to unanticipated performance. A memory read event, for example, may cause the VCO on chip to produce greater phase noise during that event. These complex interactions can be predicted by applying full electromagnetic simulation of the package and board in concert with a top-level transient or harmonic balance simulation at the circuit level.

Modern compute power can be harnessed to simulate even more comprehensive analyses. New compute architectures pack more processors into less space with large memory allowing massive simulations. Intel and AMD will deliver quad-core processors in the very near future with 64-bit architectures. Multithreaded software takes advantage of multiple processors. Ansoft has observed that many of the leaders in electronics design are rapidly adopting inexpensive Linux compute farms and a distributed computing approach. There has always been a need for parametrics, sensitivity, and optimization. The new distributed computing allows these simulations to be performed with great efficiency for model library development and sensitivity design.

The solution to these challenges has several elements that come together to solve across domain and hierarchy. Including effects of electromagnetics causes circuit simulations to get bigger with the requirement for solution in both the time- and frequency-domain. Powerful new simulation technology that integrates a high-capacity transient simulator with powerful multi-tone harmonic balance is required to simulate circuits under complex modulation and in dense wireless environments. Complex interaction at the chip, package, and board levels are simulated with full-wave electromagnetic field solvers resulting in large S-parameter blocks. New circuit simulators must be able to analyze these large blocks in both the time- and frequency-domain. New algorithms using state space modeling and model order reduction allow these simulations to be integrated into comprehensive analysis of systems. Modeling on-chip components using electromagnetics is especially important for emerging wireless applications that may have greater integration or very high frequencies. Libraries of components can be created by parametric simulation using 3D field solvers. Taking advantage of distributed processing and a new Distributed Solve Option (DSO) allows these libraries to be created with great efficiency. Finally, these simulation technologies are integrated into popular design environments like Cadence ADE™ to ensure flexibility and ease of adoption. Managing all of the complexities of 3D field solutions for boards and packages, coupled with other on-chip components, plus IC netlists in HSPICE or Spectre formats is critical. New technology that manages the design has been delivered that allows S-parameters, dynamic links to parameterized HFSS simulations, Nexxim circuit simulation, and even system-level behavioral modeling for complex waveform testbenches in a single simulation.

Design of modern wireless systems continues to create challenges for design engineers. By adoption of new strategies and tools those engineers can explore high-density designs and accurately predict system performance.