ARC International today introduces an architecture that will meet the high definition (HD) media processing requirements in a wide array of consumer devices. The ARC® VRaptor™ Media Architecture will scale from simple MP3 decode to complex HD H.264 encode using an architecture that efficiently exploits parallelism in advanced media applications. ARC’s VRaptor Media Architecture will support multiple ARC 750D CPUs with media extensions, multiple vectorized 128-bit SIMD processors, high performance streaming I/O, and domain specific accelerators. All can be connected by ARC’s new active communication channels technology. The ARC VRaptor Media Architecture will be the foundation of ARC’s next-generation Media Subsystems, the first of which will be available to system-on-chip (SoC) designers globally in early 2007.

Legacy fixed architectures aren’t well suited to meet the requirements of highly complex — yet power sensitive — media-oriented processing tasks. As an example, a generic 32-bit RISC processor could require as much as 18 GHz for standard definition (SD) H.264 encode or 5 GHz for MPEG-4 encode. ARC’s VRaptor Media Architecture leverages the power of its patented configurable technology to deliver an elegant implementation that capitalizes upon application-level parallelism. ARC’s VRaptor Media Architecture will require only 200 MHz for SD H.264 encoding, while retaining all of the benefits of a programmable solution.

Details of the ARC® VRaptor™ Media Architecture

Multiple configurations of ARC’s award-winning 128-bit SIMD processors are capable of handling a variety of media operations such as deblock filters, pixel transforms, and audio processing in the ARC VRaptor Media Architecture. Each have a rich array of arithmetic, logical, and control instructions, configurable and programmable vector and scalar registers, as well as a set of application specific instructions that are specifically tailored to accelerate complex operations. They will be connected via ARC’s active communication channels technology to optional configurable media accelerators that are capable of performing repetitive, computationally intensive tasks such as motion estimation or entropy encoding in the case of video encoding, and to VRaptor's I/O devices for DMA operations.


Because VRaptor is a heterogeneous multi-core architecture, the configurable ARC 750D CPUs, vectorized SIMD media processors, dedicated hardware accelerators, and I/O devices are programmed with the same tools and interconnected with ARC’s active communication channels technology. This will simplify the software development process and enable SoC designers to easily include codecs and algorithms over time, extending the market life of chips based upon the VRaptor Architecture.

Configurable and Scalable

The VRaptor Architecture can scale from a single configurable ARC 710D CPU up to multiple configurable ARC 750D CPUs, each with multiple media processors, multiple accelerators, and multiple I/O devices. The smallest instantiation will be less than 0.5 mm2 in a 90nm process.


Each vectorized media processor has been created using ARC’s patented configurable technology, and extended from a base configuration of an ARC 750D CPU. This will ensure instruction-level compatibility with the ARCompact™ ISA and allow support by the same toolsets that support other ARC subsystems and processors. Included are MetaWare and GNU tools, which provide extensive profiling, debug, and assembly level support. These are being enhanced to include a vectorized compiler and fast models.

Low Power

As with all ARC products, the VRaptor Architecture is being designed with low power requirements in mind, including power down features, and real time software and hardware tradeoffs.

Active Communication Channels Technology

The patent-pending active communication channels technology in the VRaptor Media Architecture is an active channel protocol that is based around Remote Invocation. It provides point-to-point links in hardware between the VRaptor cores, VRaptor accelerators and VRaptor I/O elements, and carries commands as well as data. The active communication channels technology is supported directly by new instruction extensions in ARC’s configurable ISA, and eliminates message interpretation overhead. It provides for a unified programming model that simplifies the programming overhead that is often associated with multi-processor architectures.