National Semiconductor and ARM announce the second-generation PowerWise interface (PWI) specification, which provides enhanced power-management-interconnect capability to feature-rich, multi-domain SoCs in battery-powered, handheld electronic devices. As an extension of PWI 1.0, PWI 2.0 adds multi-domain capability to address emerging needs of highly integrated SoCs. The PWI specification enables rapid deployment of advanced power management solutions in battery-powered handheld electronic devices by providing an open, industry-wide standard for the interconnect between digital SoCs and power-management integrated circuits (PMICs). The interface is specifically defined to provide master-to-slave communication, which is optimized for control of a voltage regulation system that enables system designers to dynamically adjust the supply and back-bias voltages on digital processors. The PWI specification defines the required functionality in the PWI-slave; the operating states, the physical interface, the register set, the command set and the data communication protocol for messaging between the PWI-master(s) and the PWI-slave(s). The PWI command set includes PMIC operating-state control, register-read, register-write and voltage-adjust commands. The specification also provides a provision for user-defined registers in the PWI-slave.