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Lattice Semiconductor announces its LatticeSC™ System Chip FPGA family, fabricated on Fujitsu’s 90-nm CMOS process technology utilizing 300 mm wafers. LatticeSC FPGAs have features that accelerate chip-to-chip, chip-to-memory, high-speed serial, backplane and network-data-path connectivity to provide high performance. Integrated into the LatticeSC devices are high-channel count SERDES blocks supporting 3.4 Gb/s data rates, PURESPEED parallel I/O providing 2 Gb/s speed, innovative clock-management structures, FPGA logic operating at 500 MHz, dense block RAM and Lattice’s masked array for cost optimization (MACO)-embedded, structured ASIC blocks.


Lattice Semiconductor Corporation


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