Cadence Design Systems, Inc. introduces the SoC EncounterGXL and the Encounter RTL Compiler GXL, an upgraded version of the Cadence® Encounter® RTL Compiler global synthesis technology. SoC Encounter GXL adds yield as a standard design target throughout the implementation flow to address both the 'defect' and 'process variation' challenges of advanced designs at 65 nanometers and beyond. SoC Encounter GXL addresses nanometer defect yield issues with new yield analysis and optimization capabilities embedded across the implementation flow. For yield analysis, a new command, reportYield, assesses full-chip or block-level defect yield losses based on factors such as critical area and cell yields. A unique yield prototyping capability enables users to choose full-chip floor planning strategies with visibility of yield considerations before committing to a physical architecture for the chip. For yield optimization, SoC Encounter GXL supports cell optimization in global RTL and physical synthesis using yield-aware cell libraries in either PDF Solutions' pDFm or a new Encounter format. Cadence Encounter RTL Compiler GXL helps leading-edge designers deliver smaller, faster and cooler chips in less time. New capabilities include advanced low-power synthesis with top-down multi-supply voltage (MSV) optimization, automatic physical layout estimation (PLE), top-down retiming for high-performance designs, multi-CPU superthreading to improve customer productivity, and single-pass multi-mode synthesis. Encounter RTL Compiler global synthesis is architected to concurrently optimize timing, area, and power, thus resulting in optimal quality of silicon (QoS), even under challenging low-power requirement.
Cadence Design Systems, Inc.