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Arithmatica announces its CellMath™ tools line with two standard cell-based design tools that can improve silicon efficiency. These new tools, which deliver the company’s silicon math know-how to datapath-intensive modules, include: CellMath Designer — provides a unique datapath design environment including support for integer, fixed-point and carry-save arithmetic, configurable floating-point functions, timing engine, auto-pipelining, logic optimization based on multiple proprietary microarchitectures and operator merging and logic sharing across the entire datapath; and CellMath Builder — configures a library of silicon-efficient, floating-point functions based on user performance goals and options such as bit width, internal accuracy and pipeline stages. CellMath tools generate C and Verilog models for simulation and formal verification, and technology-specific netlists for integration into chip-level netlists during physical synthesis. The models and netlists produced provide a means to formally verify the netlist to the behavioral model, relieving the significant verification bottleneck typical in complex datapath design.


Arithmatica, Inc.


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