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Lattice Semiconductor announces several ispLeverCORE Intellectual Property (IP) modules for its LatticeXP FPGAs. Easily integrated into the Lattice ispLEVER design tool suite, and optimized to take advantage of the LatticeXP architecture, the initial IP cores include Ethernet, PCI, DMA, FCRAM and DDR and target the consumer, computing and communications markets. Lattice ispLeverCORE IP modules are ready-to-use, well documented and fully supported by Lattice field and factory engineers. Complementing the Lattice ispLeverCORE IP cores are free reference designs that support a number of functions. These reference designs are available now and come with either source code or a netlist: QDR II SDRAM controller; SDR SDRAM controller; I2C bus master controller; 1553 data bus encoder/decoder; RGMII to GMII bridge; POS PHY level 3 link.


Lattice Semiconductor Corporation


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