Arithmatica and Cadence Design Systems, Inc. announce an integrated flow. Developed as part of the Cadence® OpenChoice Program, the flow includes Arithmatica CellMath silicon IP as well as Cadence synthesis technology Encounter RTL Compiler synthesis and Encounter Conformal® formal verification tools. Users can verify equivalency to design specifications, making it suitable for customers that face aggressive design and verification cycles, such as those involved in consumer electronics. The integrated flow improves silicon end-results for math-critical chip design in two ways. First, Arithmatica's work with Cadence ensures that CellMath IP, delivered typically as a gate-level netlist, is proven against the bit-accurate Verilog simulation model with the aid of Cadence's Conformal formal equivalency checking technology, which includes unique data path capabilities to verify equivalence of the behavioral model and netlist. Second, use of Encounter RTL Compiler ensures that the CellMath IP architectures are integrated and optimized within an overall chip design.