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Agilent and Synopsys Inc. announce a scan diagnostics reference methodology. The solution speeds fault localization and failure analysis for semiconductor design and test engineers. The methodology is enabled by the Agilent 93000 SmarTest Program Generator (PG) 2.2 and the Synopsys TetraMAXâ automatic test pattern generation (ATPG) solution, in conjunction with the Agilent 93000 SOC Series test platform. This combination of tools automates the bidirectional information sharing between electronic design automation (EDA) and automatic test equipment (ATE) required for scan diagnostics. TheSmarTest PG 2.2 offers a transition from the EDA environment to the capabilities of the Agilent 93000 SOC series, which speeds test development for functional and scan tests. SmarTest PG 2.2 provides a scan failure map for viewing scan failures on the 93000 SOC series in their native scan context, speeding first silicon debug. It features a simplified user interface and command-line operation, and supports industry-standard EDA input formats, including Standard Test Interface Language (STIL), Waveform Generation Language (WGL), Value Change Dump (VCD), Extended VCD (EVCD) and Core Test Language (CTL).

Agilent Technologies, Inc.

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