Traditionally, PLL characterization is a long and tedious process. A novel approach using real-time analysis promises to shorten the procedure.By Thomas Elliott
A critical step in the development of a mobile handset is the characterization or validation of the unit's internal PLL component. But it's not because the job is technically difficult, or because the measurement procedure is esoteric. Designers are frustrated by PLL characterization simply because the process is so slow.
In a world that rewards early entrants with market share, engineers are under tremendous pressure to turn out products quickly. And yet they may find themselves spending precious hours on PLL characterization alone.
Figure 1. The frequency transition of a phase lock loop..
PLLs are designed to lock on a certain frequency in a system and hold it steady. In a wireless handset, the PLL is responsible for stabilizing the two frequency endpoints when the phone switches to check for activity at alternative base stations. The handset's local oscillator might switch from 2.1 GHz to 1.9 GHz and back, for example. WCDMA technology allows a time span ranging from three slots to not more than 14 slots for this operation (a slot lasts 666 μs). The PLL's settling time a quantity that is usually specified in the standard is an important part of this allowance.
Figure 1 illustrates the behavior of a frequency-switching operation and the PLL's response to it. Frequency F1 is the nominal oscillator frequency before the operation begins; frequency F2 is the endpoint of the transition. The red line symbolizes a perfect but unachievable response: a frequency shift that takes zero time and stabilizes instantly at frequency F2. The PLL's job is to approximate this ideal as closely as possible. The black trace depicts a more realistic switching step under the control of a PLL. The operation takes time, and the frequency overshoots beyond F2 to a peak frequency (FP), and then gradually settles (after another, shallower swing below F2) to the final frequency.
Obviously it is desirable to minimize both the frequency overshoot and the settling time of the switching procedure.
The job of determining this PLL settling time falls to the designer or evaluation engineer, who usually turns to a spectrum analyzer to capture the component's response. The instrument is set for a very narrow RBW, sometimes as low as 1 Hz if the tool permits it. This setting minimizes phase noise that can affect measurement accuracy but it comes at a cost. At 1 Hz RBW, traditional swept spectrum analysis can take five minutes or more to complete its sweep.
Figure 2. Swept spectrum analyzer architecture..
Sweeping Through The Signal
A glance at a spectrum analyzer block diagram (see Figure 2) will help explain this architectural tradeoff. The local oscillator sweeps through a "span" of frequencies feeding the mixer. Each sweep produces sum and difference frequencies on the mixer's output. The resolution filter's bandwidth is set to a user-selected frequency, the RBW. Narrower filter bandwidth provides higher resolution and tends to exclude unwanted noise frequencies. The filter feeds the detector, which measures the power at each instant in time to produce a frequency-domain display plotting power vs. frequency.
Unfortunately, there is a side effect to using narrow RBW. Narrower RBW values are achieved by increasing the Q in the filter. As Q increases, it takes longer to charge the filter because its internal reactance is higher. To allow time for the filter to charge, the local oscillator's sweep cycle must be slowed down proportionally. Ultimately, a high-performance spectrum analyzer that might claim a maximum sweep rate of, say, 100 Hz at its highest RBW delivers an effective sweep rate of .003 Hz at its lowest!
Figure 3. Real-time spectrum analyzer architecture.
There is another characteristic that impacts PLL measurements made with swept spectrum analysis techniques. The long sweep time just described acquires the desired span of the signal, but assumes that the input is a rock-steady frequency spectrum that does not change. Yet frequency change is exactly what PLL settling measurements are all about. By definition, the PLL's frequency is unsteady during the time it takes to lock up and settle. Any fast-occurring changes will not be detected due to the time it takes to charge the filter, or may be overlooked simply because the sweep is not in the right place, frequency-wise, at the right time.
Figure 4. combines a conventional frequency domain spectrum window with a Figure spectrogram display.
Clearly there is a need for an alternative approach to PLL settling time measurements. A better method becomes clear just by thinking about the PLL signals in question. Their dynamic nature says that the measurement instrument needs to look at a whole span of frequencies all at once, rather looking separately at a series of individual frequencies, and then piecing the information together. What is needed is a technique that can provide an ongoing, full view of a frequency band wide enough to encompass the entire range of variations as the PLL stabilizes.
This implies a whole different acquisition architecture. The traditional concept of a slow, deliberate "sweep" across the frequencies of interest would no longer apply. This innovative testing methodology has arrived and is quickly taking the lead for spectrum acquisition in the presence of fast moving, time varying signals. These methods, sometimes described as a "real-time spectrum analysis" can capture the signal at hundreds of frequency points simultaneously. The architecture is elegantly simple, as shown in Figure 3.
There is still a resolution filter and a detector, but the local oscillator and mixer are gone no longer needed. There is no more sweeping from frequency to frequency. The entire battery of filters sees the full signal span at once, and each filter delivers its segment of the spectrum to its own local detector. The instrument used to generate the graph in Figure 1 has 800 filter/detector pairs. This number equates to the number of pixels across the width of the display screen. In other words, every acquisition takes full advantage of the maximum display resolution.
Since the process is not one of sweeping across the RF input signal and building an image from serially acquired frequency sweeps, this parallel architecture can reset quickly and gather new analysis. In contrast to the swept analyzer's multi-second sweep rate, the parallel analyzer can perform hundreds or even thousands of acquisitions per second, depending on the RBW setting. The parallel acquisition ensures the chance that the spectrum analyzer will indeed catch the dynamic frequency variations that occur as the PLL settles and real-time guarantees it.
Figure 5. In a spectrogram, the viewer looks "downward" on an accumulation of spectrum acquisitions.
Information-Rich Displays Bring Out PLL Details At A Glance
This opens the door to information-rich display formats, particularly the spectrogram. A spectrogram is a visual history of many acquisitions. The acquisitions are "stacked up" such that trends and aberrations are easily visible. Figure 41 is a display that combines a conventional frequency domain spectrum window with a spectrogram display.
The screen depicts an acquisition-actually a series of very fast, repeated acquisitions of a simulated cellular phone switching operation of the type described earlier. The actual device is a handheld two-way radio. Keying the radio to transmit is equivalent to the cell phone's frequency switching as it searches for an alternate base station. The radio includes a PLL to perform the same stabilizing role as the cell phone's PLL.
In the left window, there is a spectrum where the center frequency is 467.6 MHz; the carrier frequency. The signal is narrow and stable, but this is just one instant in time. In truth, the carrier frequency moves around before settling at the desired frequency. Thanks to the unique combination of real time spectrum analysis, long capture memory, and the frequency mask trigger, an analyzer can capture all the information as the carrier signal settles onto its new frequency. Frequency mask trigger allows the analyzer to only trigger once the carrier signal reaches a certain frequency (defined by the user).
It is at this point that an analyzer would begin storing information to memory, resulting in the capture of only the information that is meaningful to the user. Once information is stored into memory the user can view the spectral content in the frequency domain for any point in time by simply using the marker to select any point in time on the spectrogram. Thus this combination enables the designer to have a complete view of carrier as it changes over time, from one frequency to another.
Note the similarity between this spectrogram and the curve plotted in Figure 1. Here, the axes are reversed, but the basic shape of the frequency-settling curve is exactly as predicted. This curve is a plot made from many frames' worth of spectrum displays, where one frame is equivalent to the information shown in the left-hand window. The frames are stacked up, with the oldest information at the top. In a sense, we are looking straight down on this stack, at the "tops" of a series of peaks. Where the signal has spread in frequency, the line is wider (see Figure 52). Where the frequency varies, the line follows it across the X-axis of the spectrogram.
The spectrogram delivers a vast amount of detail about the PLL's settling behavior. Importantly, it provides a perspective that conventional swept spectrum analysis techniques cannot match. It is easy to see trends and the "big picture." But there is much more to be learned from the acquisition.
Drilling Down Past The Spectrogram's Top Layer
The top-level view of the spectrogram is made up of hundreds of spectrum frames. Each frame is an entity that contains 1024 samples that can be processed and analyzed. The processed information can be reassembled to provide details never before seen.
Figure 6. An FM-demodulated plot of PLL frequency behavior.
Figure 6 shows a detailed, FM-demodulated view of a PLL's frequency behavior as it breaks lock, settles, and re-locks to the end frequency (equivalent to F2 in Figure 1). The data was compiled from a succession of frames as seen in the earlier spectrogram.
In Figure 6, frequency is on the vertical axis while time is on the horizontal. The window encompasses 9.93 milliseconds of time. The PLL's frequency starts at one frequency on the left one division above the center, then changes to 2.5 divisions up, goes to full scale ( 800 kHz), then to a new, steadier frequency on the center of the display that is rather noisy for the remainder of the settling time. The two small spikes that occur during the noisy period imply that the PLL has again broken its frequency lock-an aberration worth looking into.
Is It Truly Settled?
It is also possible to demodulate the phase (PM demodulation) of the spectrum frames. This view can reveal behavior that is not visible with any other type spectrum view, yet can dramatically affect the PLL's response. The information is available only because real-time analysis techniques can capture a broad span of frequencies all at once.
Figure 7. A phase-modulated plot of the "settled" PLL frequency. The 20-degree phase shifts can contribute to bit errors in quadrature-modulated devices.
Figure 7 is a plot-depicting phase changes over time on the settled signal. In a perfect world, the plot would be a ruler-straight line centered on the vertical scale at zero degrees. Instead we see constant phase deviations of 20 degrees and more, likely caused by the VCO loop times.
What effect is this having on the circuit? It depends on the circuit's phase tolerance. In a QPSK design, for example, each bit's value relies on its proximity to one of four quadrature points spaced 90 degrees apart. There is a tolerance of no more one-half the distance between any two quadrature points or 45 degrees. Clearly, the 20-degree phase shifts in Figure 7 are a problem-they consume almost half of the phase error budget. It is beyond the scope of this discussion to troubleshoot the problem to its conclusion, but the important point is that the presence of these phase shifts is completely unexpected before the phase-demodulated analysis.
PLL devices are a key component in every mobile phone as well as other RF network elements. To the PLL IC designer, there is likely to be pressure to make continuous incremental improvements to meet competitive pressure. To the mobile phone designer, it is important to thoroughly understand the frequency-changing response of any PLL device being considered for adoption in emerging products. Both of these users need a means to capture and analyze the real behavior of the PLL device in question.
Traditional swept spectrum analysis techniques are giving way to real-time spectrum acquisition, which acquires much more data, faster, even at narrow RBW settings. There is new generation of tools that finishes the acquisition in a fraction of a second rather than minutes and provides a continuum of spectrum traces that are the basis for information-rich spectrogram displays. The data can be processed with FM demodulation or PM demodulation to bring out eye-opening details about phase instability and more. Most importantly, these analysis can quickly reveal behaviors that would otherwise go undetected, waiting to disrupt a project late in the design cycle-or even when the end product is in users' hands.
1. The screen images used in this article are chosen to most clearly illustrate the principles being described. They are not acquired from actual cellular frequency switching operations. 2. The shape of the spectral plots is exaggerated here to emphasize their effect on the spectrogram trace.
About the author
Tom Elliott works in Tektronix' Wireless Product Line (WPL) as a product manager. He is responsible for wireless field test and spectrum analyzer product management. He has been working in the high-tech industry for more than 28 years of which 15 years have been spent focused on RF sales, service and applications training. Elliott holds a Masters in Adult, Postsecondary, and Continuing Education (MSEd) from Portland Sate University and a Bachelor's of Science in Electrical Engineering (BSEE) from the Oregon Institute of Technology (OIT).