Modern synthesis platforms create optimal designs based on performance specifications. An added benefit is that the designer is able to simultaneously evaluate the trade-offs between higher performance and reduced design margins.

By Navraj Nandra

New and efficient methodologies for verifying the design robustness of analog and RF designs — designs that are automatically created using a synthesis platform are making a big impact on today's designs, as well as bottom lines. The synthesis platform is capable of creating the optimal design based on performance specifications. An added bonus of synthesis platforms is that the designer is, simultaneously, able to evaluate the trade-offs between performance and design margins.

Figure 1. Using multiple Monte Carlo simulations for design centering. Once a user has entered the performance specifications, the synthesis platform will optimize the design for both component sizing and layout synthesis by formulating circuit equations as convex optimization problems. The challenge is to prove that the synthesized design is correct by composition and that it meets all of the predicted performance requirements under all operating conditions — without having to resort to exhaustive silicon verification for every instantiation.

To guarantee the robustness of each optimized instantiation validation program is presented that incorporates a certification pyramid. This has been used to qualify 0.18 μm and 0.13 μm synthesis platforms. This new methodology avoids both the very arduous task of setting up and running Monte Carlo simulations and the expense of multiple silicon fabrication runs.

Some Background

Since pressure is always on to miniaturize real estate, maximize functionality and minimize power, reliability margins have narrowed. This raises the production bar and further makes the production of robust analog and RF integrated circuits a very complex task.

Circuit performance depends on the transistor behavior. Small variations in the manufacturing process can result in dramatic changes in circuit performance.

During production, technology parameter variations can make circuits fail. The goal for design for manufacturability is to center the design so that the majority of the fabricated circuits fall within the performance specifications, while keeping the area overhead minimal. This translates into a need for accurate transistor models over different process corners.

Figure 2. Transistor layout showing the important analog constraints.

Another important concern in mixed-mode ICs is substrate noise coupling due to, for example, fast switching digital circuitry that can deteriorate significantly the value of the sensitive analog signals. Also careful layout to reduce device mismatches and parasitics is crucial to guarantee correct circuit behavior. Unlike digital circuits, the designer has to keep in mind a large number of performance specifications, making it time consuming to redesign an analog block. For designs manufactured in 0.13 μm and below HCE, NBTI and STI stress effects must be addressed in order to gain maximum analog and RF performance. Although commercial tools exist to manage the reliability targets the accuracy of these models is inadequate.

Design Robustness

Design robustness is achieved by considering all of the factors mentioned. These are the factors that can adversely affect manufacturing yield and performance. They are incorporated into the synthesis platform.

Figure 3. Certification Pyramid

From the same equations that describe the circuit behavior and performance specifications, the spread of technology variables is also incorporated.

What this means is that if designs on the boundary are feasible then the implication is that verifications do not need to be run for every new instantiation of a synthesized design as long as that design is within the feasibility set. The basis of this theory is used in the selection criteria for the certification pyramid. A traditional approach to improve the yield is to use run multiple Monte Carlo simulations and this is covered in the next section.

Taking The Gamble Out — Yield Optimization the Hard Way

Monte Carlo analysis creates a batch of circuits populated with tolerance components and statistically tests circuit performance. Each circuit is constructed of many components randomly selected from populations matching the user-defined tolerances and distribution type. The result is a distribution plot of design constraints. The data can give insights into the reliability, cost, and the ability to manufacture the circuit. The idea is to use multiple Monte Carlo simulations2 inside an optimization routine (See Figure 1).

The Monte Carlo Approach

The loop is comprised of an optimizer proposing a candidate circuit and the evaluation engine, evaluating the quality of each candidate. This keeps looping until the specification is met. This is known as the design centering method and can only be used, realistically, in post-design optimization. Commercially available tools use SPICE and a numerical search engine or a bunch of numerical search engines. The optimizer can be:

• The design engineer

• Simulated annealing

• Newton's method

• Any other type of classical optimization methods

The method is CPU intensive and virtually impossible to handle a circuit with more than a few tens of transistors. Also, the method requires an analog designer and optimization expert: the experienced analog designer to input the SPICE deck and test benches; the optimization expert to select the step size, the search space and the search method. Additionally, Monte Carlo is difficult and can take forever.

Convex Optimization Problems

In Figure 3, it is shown that both transistor behavior and performance measures for analog design, such as RF components, phase locked loops, data converters, etc. can be formulated as posynomial functions of the design variables. As a result, these design problems can be formulated as geometric programs, a special type of convex optimization problem for which very efficient global optimization methods have recently been developed.

The synthesis method is therefore fast, and determines the globally optimal design. In particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected.

Methods to solve convex optimization problems have several advantages when compared to general-purpose optimization methods. They find the globally optimal solution, which can be computed extremely fast, even for large problems. If a solution exists, convergence is guaranteed. The following paragraphs describe geometric programs in both standard and convex form.

Let x be a vector (x1, ..., xn) of real, positive variables. A function, f, is called a posynomial function of x if it has the form (Equation 1):

Equation 1


cj<= 0 and αij R. When there is only one term in the sum, i.e., t = 1, we call fa a monomial function.

A geometric program is an optimization problem of the form (Equation 2):

Equation 1


fo, ..., fm are posynomial functions and g1, ..., gp are monomial functions.

A geometric program can be reformulated as a convex optimization problem, by changing the variables and considering the logs of the functions involved.

In modeling a circuit with geometric programming, the design space is represented as a convex set — convex problems have a special property: their feasible sets are convex.

Robust Analog IP Creation

It is well known that the statistical variations in electrical parameters, such as transistor gain, are due to variations in the fabrication process and can impact circuit performance and yield. By ensuring tight coupling between fabrication and circuit design the synthesis platform can produce robust designs.

Process Variations

These are due to random manufacturing variations and traditionally incorporated into process corner models. For example, during device manufacturing, non-uniform conditions in the diffusion or deposition of dopants can result in changes in the oxide thicknesses and diffusion depths. Changes in the oxide thickness and in the dopant levels in the substrate, poly, implants and surface charge will affect the value of the threshold voltage. The resolution of the photolithographic process can cause W/L variations in MOS transistors. Changes in these parameters cause electrical parameters to vary, such as sheet resistance and threshold voltage. This affects the design process.

For example an operational amplifier is constrained by a unity gain bandwidth of 500 MHz for a particular power consumption. In order to meet this constraint the design can be optimized over multiple process corners. In addition, supply voltage variation and factors such as resistance variation can be included. Table 2 lists the some of process related specifications that are included as part of the optimization routine in the synthesis platform.

The following paragraph describes the parameters listed in Table 1. The percent variation in supply voltage can be set, for example to the value of 10%. On a 1.8 V supply, the optimization ensures that all of the specifications are met at both 1.62 V and 1.98 V (Vdd± 10%). For example, while power consumption may be worst-case at 1.98 V, saturation margins will be worst-case at 1.62 V. The percent variation of any on-chip resistors: if this value is 20%, the optimization ensures that all of the specifications are met at resistance ± 20%. Since resistors can be used in voltage reference and loop filter circuits, and therefore critical to the manufacturing yield, both reference current variation and stability margins are taken into account during optimization.

When the process corners for a robust design are selected, the following occurs:

• Each specification must hold for every process corner and the value of the specification reported is the worst-case value for the set of corners chosen.

• The reported value for the objective is the worst case over the selected corners.

Matching Parameters

In addition to the process variations that can occur between different wafer lots, device performance can also vary between devices placed on the same die.

Transistor and current mismatch has a big impact on the performance limits of analog designs. Typical performance parameters such as the resolution of data converters, the CMRR and PSRR of operational amplifiers depend on transistor matching. These matching (or mismatching) effects can seriously impact design robustness.

The mismatch in transistor threshold voltage is used to calculate several components of noise in the design. The mismatch is modeled as the variation of the threshold voltage for a particular transistor and the nominal threshold voltage for the process. This is modeled as a random variable with the variance inversely proportional to the area of the device. The standard deviation in the current is modeled as the percent variation between the saturation current Id,sat for a particular transistor and the nominal Id,sat for the transistor in the process. Transistors on opposite sides of a differential pair will exhibit mismatch in threshold voltage and saturation current due to random variations that occur during fabrication.

Noise and Power Supply Variables

Factors such as noise and variations in the power supplies have a larger influence on the performance of analog and RF designs as opposed to digital designs. For example the first order parameters, such as gain and bandwidth, of an analog design may well be met. But due to noise, specifications such as the SNR cannot be realized.

The optimized design must be robust in noisy environments yet be able to reject power supply variations. In order to meet these constraints the synthesis platform allows the user to tune the design to any environment. The following presents the power supply rejection constraints using, as an example, the accumulated jitter in a PLL from a 10% Vdd step on Vdd.

Once this step is applied, the instantaneous phase error between the ideal reference clock and the output clock will begin to accumulate. After some time, the loop will respond and begin to drive these signals back into phase alignment. This specification represents the worst-case instantaneous phase error following the voltage step. For robustness, the rise time of the voltage step is assumed to be much shorter than the reference period. In reality, any on-chip voltage step would likely occur with much slower rise times and fall times. This would result in much better performance than this specification would indicate.

In fact the design may be more vulnerable to one type of noise than another. The idea is that the user evaluates the environment and determines the greatest vulnerability. Then, set the constraint to a low value, determines the next greatest vulnerability and set it to a little higher value. The optimization routine tries to match all the constraints. Setting the most important constraints to the tightest values and the least important constraints to loose values gives the optimization routines a greater ability to meet the requirements.


The synthesis platform includes all the parasitic effects at the start of the optimization process by building them into the models. This eliminates the uncertainty from the design process. The models are built to handle the signal integrity issues such as the unwanted resistance, capacitance and inductance effects associated with devices and their interconnects.

Effects such as cross-coupling between neighboring interconnect lines are modeled and if these impact the performance the routing algorithm in the synthesis platform will accommodate this into the layout.


The synthesis platform uses geometric programming to control the layout to achieve the system objectives. These issues relate to the device, block, floor plan and routing. In order to achieve the performance required in analog and RF circuits the following layout constraints are considered.

Symmetry constraints: A component can be constrained as to be centered about a vertical or horizontal axis. Two components of the same size can be constrained to be mirror image of each other about an axis.

Mirroring nets: Net can be mirrored about an axis.

Net matching: Tabs (layout extensions) can be added to routes to equalize the total horizontal metal lengths and the total vertical metal lengths of two nets.

Alignment: Two components can be constrained to align to each other along the top, the bottom, the left, or the right.

Capacitance constraint: this limits the capacitance between the routes and the substrate by bounding the length of the routes. IR drop considerations: The router will try to size the power rail to limit the IR drop to a specified amount.

One other important consideration built into the device generators is interdigitized drain. This reduces the device capacitances, ensuring symmetrical current direction, guardrings and dummy structures. An example of a device generated for an analog or RF design is shown in Figure 2.

The Value of a Certification Program

To ensure robustness of the overall solution, rigorous certification methodology is applied. The certification pyramid is divided into four levels (See Figure 3).

The selection of the specifications in level one was based on design of the experiment and heuristic methods. The design specification space was covered with an uncorrelated sweep of the main specifications. In the case of the PLL this was jitter, power and static phase error. Heuristic criteria were used for the definition of a grid that took into account the correlation among the specifications.

The strategy used in qualifying the synthesis platform functionality and performance in level one involved performing a series of optimizations. The process involves increasing the number of test scenarios from three to 49. The test scenario was defined as selecting process corners from one to seven, varying the supply voltage by 10% from nominal, varying the on-chip polysilicon resistances by 20% from it's nominal value and selecting three VCO frequencies.

The goal of level two was to qualify the accuracy and functionality of the optimized designs from level one by examining the correlation between the parameters that can be extracted from SPICE simulations and the predicted ones from the synthesis platform. Particular emphasis was placed on the SPICE simulations for the analog blocks. For example, for the VCO, the following were simulated: power consumption saturation margins, frequency range, kVCO gain and PSRR, (kVdd) at both low and high frequencies.

Level three was the last stage in the qualification and the goal was to provide the final correlation between the specifications predicted by the synthesis platform and the extracted simulations at the macro level. To ensure that the specifications were ready for fabrication, the synthesis platform was required to produce GDSII data that was free of layout versus schematic errors. It also was required not violate any of the semiconductor design rules.

One of the main issues that can degrade performance or even cause design failure for analog designs is the affect of parasitics. Level three qualification included confirmation of the parasitic prediction for the automated GDSII layout. Selection from the level 2 pools of specifications was based on covering frequency and low jitter range, on low power PLLs, for corresponding frequency range, for silicon samples that would cover the following applications: consumer multimedia; wireless and wired communication; microprocessors and ASICs.

Level four, the final step in the certification of the synthesis platform, is the silicon validation. Here the goal is to confirm the rigor and robustness of level one through three qualification with validation, in silicon. Level three designs were selected. Tables 2 and 3 show the silicon results of two PLL's from level four. Tables 1 summarizes the key parameters of two PLL's produced using Miró on TSMC's 0.18 μm logic process. The Miró results are shown for worst-case process, voltage and temperature variations. The GDSII layout was produced in a matter of hours and submitted directly to the foundry without any changes.


This article has presented a new and efficient methodology that optimizes designs based on performance specifications and simultaneously ensures a robust design ready for manufacture. It offers an elegant solution that designers can use to efficiently and cost-effectively bring a product or device to market.


1. Hershenson, M. "Efficient description of the design space of analog circuits" 2. G. Debyser. G. Gielen, KUL, Belgium, "Efficient analog circuit synthesis with simultaneous yields and robustness optimization" 3. Hershenshon, M., Boyd, S., Lee, T.H., "GPCAD: A tool for CMOS op-amp synthesis", IEEE/ACM Conference, San Jose, CA Nov. 1998


ASIC - application-specific integrated circuit CMRR - common mode rejection ratio CPU - central processing unit HCE - Hot carrier effect IC - Integrated circuit MOS - metal-oxide semiconductor NBTI - negative bias thermal instability PLL - phase-lock loop PSRR - power supply rejection ratio SNR - signal to noise ratio STI - shallow trench isolation VCO - voltage-controlled oscillator