XIP vs. Code Shadowing Architecture

By Pascal Deriot, Micron Technology, Inc.

Growing demand for easy access to audio, video, and text has led to a proliferation of feature-rich wireless products. For example, cellular phones are now equipped with cameras and mini-camcorders. They have the capability to send and receive images and e-mails; download and play music files and sounds, as well as games or business applications; and stream video. The introduction of this new functionality in 2.5G and 3G phones is spurring demand for more diverse memory, while also stimulating the replacement market.

To store this type of feature-rich content, handset manufacturers need innovative architectures. Possible solutions include:

     1. Adding a removable media device, i.e., an external memory card (MMC, SD, memory stick cards) to store huge files of music or video content.

     2. Using both NOR and NAND Flash devices on-board; one dedicated to code storage and code execution (NOR), and one to data storage only (NAND).

     3. Using NAND architecture with a NOR interface.

     4. Increasing the size of the NOR-only Flash on-board to store both code and data.

     5. Switching to NAND-only Flash architecture, so code and data are stored into NAND and code is copied from NAND to RAM for execution.

Figure 1. Architecture Comparison of XIP vs. Code Shadowing

Of these five solutions, NAND technology (solution 1) is the Flash card industry's choice for a cost-effective, solid-state hard drive, ideal for playing music or video files. For handset manufacturers, however, the choice between NOR-only/execute-in-place (XIP) architecture (solution 4) and NAND-only/code shadowing architecture (solution 5) is still largely up for debate.

This article analyzes two different architectures, XIP and code shadowing, by comparing two different memory subsystems in terms of throughput, power consumption, reliability, and cost. It also looks at those architectures in terms of handset design considerations and the memory requirements of those applications. Given the conflicting design priorities between power consumption, bandwidth, space and cost, the traditional NOR-only Flash architecture emerges as the most attractive solution for low-end/mid-range 2.5G phones.

Defining XIP and Code Shadowing

Traditionally, NOR architecture is known for storing code and NAND architecture for data storage. Therefore, for 2G handset designs requiring code storage and moderate data storage (consisting of numerous small and frequently accessed files), NOR Flash is an effective solution because it is partitioned for both code execution and data storage. The introduction of multimedia features, however, prompted handset manufacturers to consider NAND-only, on-board solutions because the balance between code and data spaces is inversed, creating larger and infrequently accessed files.

XIP architecture, named for the speed at which a NOR Flash device allows the processor to execute the code directly out of the Flash device, is based on a NOR-only device and has been largely adopted by handset manufacturers because it meets the following requirements:

•Real-time applications: fast random access of 60 ns to 70 ns matches the determinism and latency constraints of cellular phones

• Power consumption: low operating voltage of 1.8 V and very low active and standby currents

• Bandwidth: access time of 60 ns to 70ns page mode, or 66 MHz to 80 MHz synchronous burst mode

• Space: multi chip package enables two, three, or more die to reside in a single package

• Cost: leading-edge process geometries, large portfolio with small/high densities, and small area for data storage.

Figure 2. Throughput and Power Consumption Comparison of XIP and Code Shadowing

Due to its small cell size, NAND Flash memory is an attractive alternative for data storage on-board. However, in many systems the use of conventional NAND Flash technology requires extra hardware and software design effort and additional power. NAND uses a serial architecture and is characterized by a very slow initial access to pages of information and therefore is not used as XIP architecture. (Real-time applications require fast context switching, allowing immediate access to execute code to the memory.) The code needs to be moved from the NAND device to the RAM (SDRAM or PSRAM) device to run applications. This code shadowing is achieved one of two ways:

• Copy all the code area at boot-up from the NAND device to the RAM (SDRAM or PSRAM). An overhead of 100 percent of the code space is reserved in the RAM space to execute applications.

• Copy-on-demand the application for execution (demand paging operation) from NAND to RAM. This reduces the overhead of RAM space by almost half (because only 50 percent of the code space needs to be reserved in the RAM), but it also increases the complexity and latency of dynamic downloading.

Memory Subsystem Alternatives

Figure 1 shows a comparison of XIP and code shadowing architectures. In the XIP approach, high-speed NOR Flash technology is used for data storage, code storage, and application storage, as well as code execution. In this subsystem, data and code are stored in the NOR Flash device and a CellularRAM device serves as a work area only for temporary storage, variables, and additional programs.

In the code shadowing approach, NAND Flash technology is dedicated to permanent data storage, code storage, and application storage. In this subsystem, data and code are stored in the NAND Flash device and code is downloaded to a Mobile SDRAM device for execution; the Mobile SDRAM device is used as a work area for temporary storage, variables, and additional programs, as well as to execute code (OS kernel and programs).

Figure 3. Benefits of XIP vs. Code Shadowing

System Analysis

The analysis of these two memory subsystems relies on the following assumptions:

• Host system: 2.5G cell phone (including entertainment capability)

• 120 megabytes per second (MB/s) memory throughput requirement

• One processor chipset, along with one memory subsystem

• Memory bus width: 16 bits

• Memory bus operating frequency: 80 MHz for NOR Flash; up to 104 MHz for CellularRAM products and Mobile SDRAM

• NOR Flash technology is single bit per cell, which achieves a maximum clock frequency of 80 MHz

• Power supply (core and I/O): 1.8 V

• Cache line length: 32 words

• Code fetch accesses: 70 percent

• System data accesses (no user data accesses were considered): 30%

• 70 percent READ accesses

• 30 percent WRITE accesses

Throughput and Power Consumption


The throughput computations are based on the following model:

• Internal register hit = 70 percent for SDRAM (pipelined architecture optimizes the latency between burst accesses)

• Burst time (ns) = initial latency + 15 clock cycles

• Throughput megabits per second (Mb/s) = 32 bytes/burst time

The XIP solution offers fast code execution with no RAM overhead. It achieves up to 142 megabytes per second (MB/s) with an 80 MHz NOR Flash plus a 104 MHz CellularRAM device.

Although the code shadowing architecture executes very fast from DRAM, 198 MB/s at 104 MHz, it is penalized by a latency each time a new program needs to be copied into the DRAM for execution.

Both memory subsystems provide throughput exceeding the requirements of 2.5G platforms, approximately 120 MB/s. Therefore, the key criteria appears to be power consumption.

Power Consumption

In comparing XIP and code shadowing, an accurate computation of power consumption must take into consideration the status of each device in each of the three cellular phone operating modes. A commonly accepted use profile for handsets is as follows:

• Sleep Mode = 90 percent (the standby current is used for NOR Flash, NAND Flash, and CellularRAM devices; self refresh current is used for Mobile SDRAM).

• Idle Mode = 6 percent (the standby current is used for NOR Flash, NAND Flash, and CellularRAM devices; auto refresh current is used for Mobile SDRAM).

• Operating Mode = 4 percent (read current is used for NOR Flash, NAND Flash, CellularRAM devices, and Mobile SDRAM devices).

Based on these computations, XIP architecture shows a strong advantage in terms of power consumption. The code shadowing architecture actually increases the system power consumption by up to 150 percent, which greatly reduces the battery life of a cellular phone.

This power increase illustrates the intrinsic limitation of the code shadowing approach. Although standard operating systems such as WinCE, Pocket PC, and Symbian expect to support the shadowing model in coming years (which will enable the implementation of dynamic loading feature and reduce RAM overhead), the NAND subsystem will still require a larger Mobile SDRAM density than the XIP model. It is also expected that the dynamic loading feature and high-speed transfers from NAND to Mobile SDRAM will increase overall power consumption. Figure 2 summarizes the throughput and power consumption comparison between code shadowing and XIP architectures.


The NOR-based memory subsystem ensures the integrity of the code and system data. The NAND-based memory subsystem, on the other hand, requires a dedicated NAND interface on the baseband chipset, combined with a software controller, to handle the ECC and the mapping of false blocks. The NOR Flash memory plus CellularRAM subsystem appears to provide the data integrity required by a wireless system without any additional hardware or sophisticated software changes.

System Cost

Although the manufacturing cost of NOR Flash memory is higher than NAND, a cost comparison of the two must consider the impact of adopting the code shadowing model into a system design. Design considerations include:

• Increased RAM densities (approximately twice that used in the XIP model)

• New DMA controller with eSRAM in the baseband chipset to ensure fast transfers between the NAND device and the Mobile SDRAM

• A dedicated NAND interface in the baseband chipset, along with a software controller, to handle the ECC and the mapping of unusable blocks

• Separate buses for Mobile SDRAM and NAND to ensure high throughput

• Sophisticated FFS to manage dynamic load, which increases the work

• Increased battery capacity; code shadowing model decreases the battery life by 60 percent (based on 90-6-4 use profile) compared to a traditional NOR-based XIP solution.

The adoption of a code shadowing model is much more complex than the proven XIP solution and therefore more risky, particularly in terms of time to market and availability.

Table 1 highlights the benefits of a XIP memory subsystem, including:

• Significant increase in battery life

• No change in the hardware system (except the management of two clocks to increase the bandwidth)

• Very high throughput, compatible with 2.5G cellular phone requirements


Running at 104 MHz, with an 80 MHz NOR Flash, CellularRAM technology offers balance of throughput, cost, and power consumption for traditional XIP systems:

• Very competitive bandwidth of 142 MB/s

• Significant increase in battery life, compared to a code shadowing architecture (104 MHz)

• Optimized system cost architecture:

     Time to market

     Proven XIP system (no hardware or software complexity overhead)

     Reduced pin count, using the same burst bus

     Easier PCB layout

An XIP architecture leveraging NOR Flash and CellularRAM technology offers a solution to the code shadowing architecture based on a NAND Flash and Mobile SDRAM combination and a suitable memory solution for the next generation of 2.5G cellular phones (See Figure 3).