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The family of "no latch" monolithic dual junction FETs (JFETs) provide an exposed substrate connection via an external pin, allowing designers to bias the substrate with a positive potential to prevent a latch-up condition. There are more than 20 devices in this family. The devices offer a range of breakdown voltages from – 25 V to – 50 V. Offset/drift voltage ranges from 40 mV down to 5 mV. This tight VGS matching minimizes errors in front-end amplifiers. A range of gate-to-source cut-off voltage ratings from – 0.5 V to – 6 V gives designers a choice of devices to suit their specific applications.

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