By: Michael T. Moore, Senior Applications Engineer Cypress Semiconductor

Many communications standards today utilize serial links as their primary channel. These standards use different frequencies of operation, which may cause headaches for designers who need to use different PHYs to support each standard. By using variable rate multi-gigabit serial links, a designer can use one PHY across multiple designs supporting different standards, simplifying the design and qualification process.

Standards used in communication system design
Some of the more popular communication technologies currently in use and in development are described here, along with their advantages and disadvantages.

Fibre Channel
Fibre channel is an established distributed I/O interface, used in server to disk storage interfaces. It has low latency and high bandwidth efficiency, due to its low software overhead. Fibre Channel resembles Ethernet but lacks the IP stack.

Fibre Channel delivers a bandwidth of 100-200 Mbytes/sec today, using a 1 or 2 Gbit physical layer.

Gigabit Ethernet
Gigabit Ethernet (802.3z) is an extension of the popular Ethernet (802.3 10 base) and Fast Ethernet (802.3u 100 base) standards. Gigabit Ethernet (802.3z) extends the data-rate and signaling conventions defined for the earlier standards to the 1Gb/sec rate, and is backward-compatible with the earlier versions of Ethernet. The Gigabit Media independent Interface (GMII) is defined for a variety of media fiber-optic media types, as well as for copper cable.

Both Gigabit Ethernet over fiber (802.3z) and Fibre Channel use 8B/10B encoding to provide an equal transition density of 1's and 0's in the data stream. This is to ensure that the clock can be recovered from the data.

Other Standards
SMPTE is a serial standard for video communication. SMPTE-292 operates at a rate of 1.482 Gbps, and one application is to carry uncompressed HDTV information.

Frequency ranges covered by commonly used standards

Figure 1: Bandwidth requirements for common port-side and backplane standards today

From this table we can see that commonly used standards on the port-side and backplane cover a wide frequency range. It is advantageous to use a single device to cover several of these frequencies, rather than require several different devices to support these standards. Variable rate multi-gigabit serial links offer the best choice of flexibility, performance and time to market. These devices may be used on a line card that supports several standards through programmable logic, where a common PHY can support all of them.

Flexible physical layer (PHY) devices
As an example of a flexible frequency PHY, the Cypress HOTLink® II provides 4 serial channels, operating from 0.2 to 1.5 Gbps, with an integrated receive framer for single or multi-byte alignment. It can directly interface to standard fiber-optic modules and can also directly drive copper cables and circuit board traces for maximum flexibility. It offers combined serial bandwidth from 200 Mbps to 6 Gbps, on a single device.

Implementing the interfaces for these standards
To implement these interfaces with the serial transceiver, integrated SERDES with programmable logic offers the best choice of flexibility, performance and time to market. The 'Frequency Agile' Programmable Serial Interface (PSI) offers programmable logic with abundant high-speed memory, and multiple channels operating from 200 Mpbs to 1.5 Gbps. It supports multiple standards including Fibre Channel, Gigabit Ethernet, ESCON, DVB and SMPTE. The interface logic for these standards may be implemented in the programmable section of the device, and the PHY provides the high-speed serial interface.

The 'Frequency Agile' PSI provides high speed and flexibility for such applications as backplanes for storage area network (SAN), wide area network (WAN), wireless infrastructure (WIN) and local area network (LAN) switches. This highly integrated device combines a SERDES, programmable logic with abundant memory, and boot flash into a space- and power-saving, single-chip solution that ease board design. Designers have the flexibility of using its four data channels independently or taking advantage of channel bonding to form a wider data path.

Figure 2: CYP15G04K100 'Frequency Agile' PSI architecture

Roadmaps to the next generation
Both Gigabit Ethernet and Fibre Channel have defined roadmaps for next generation technology. Fibre Channel is expected to reach 1.25 GBytes/s in 2002 with a physical layer operating at 10Gbit/sec. The IEEE 802.3ae 10-Gigabit Ethernet specification will extend the Ethernet standard by a factor of 10 (in terms of speed). A new Fibre Channel spec (2X Fibre Channel) operating at twice the current speed is also awaiting adoption.

10 Gigabit Ethernet
The IEEE 802.3ae 10 Gigabit Ethernet Specification is a new standard in progress that continues the evolution of Ethernet (in terms of distance and speed). The IEEE 802.3ae standard defines two interface standards between the MAC and PHY layers. The first is the XGMII (10 Gigabit Media Independent Interface. The second interface for the 10 Gigabit Ethernet standard is called the XAUI (pronounced "Zowie"). XAUI uses 16 lines (four times 2 pairs of differential signals) for up to 20 inches, versus the 74 required by the XGMII bus for up to 3 inches.

Features of the XAUI interface
XAUI specifies a narrow but fast data pipe that could use standard CMOS ICs or become embedded in ASICs. XAUI specifies 4 bit-streams, each running at 3.125 Gbps with a total of 12.5 Gbps. The XAUI specification uses 8B/10B encoding, allowing a data throughput of 10 Gbps, enough to satisfy the requirements of both 10 Gigabit Ethernet and SONET/SDH OC-192/STM-64. XAUI defines MAC and PHY layers, similar to Ethernet. This supports transport on PCB traces, short wires and optical fiber. XAUI is a self-timed interface, where the clock is encoded in the data stream, eliminating clock-to-signal skew. XAUI also has a feature were any skew between the four lanes are removed using a synchronization circuit.

Advantages of the XAUI interface
One of the advantages of the XAUI interface is to enable distance extension from the MAC device to optical modules. In addition, the XAUI interface simplifies link design across multiple jitter domains and reduces the number of interface signals. The XAUI interface is well suited to implementing 10 GigE backplane connections in a chassis environment and for directly driving an optical module.

XAUI features make it particularly well suited for high-speed backplanes. It permits a high density of lines on a backplane as each XAUI channel uses only 4 lines. This is considerably lower than parallel backplane solutions, such as PCI. XAUI offers better signal integrity and does not pass through the connectors and transition points along a backplane used in parallel backplanes.

As well as providing an inside-the-box backplane solution, XAUI also offers a relatively inexpensive box-to-box solution. In 10G systems, connections between boxes require the use of optical fiber and expensive 10G laser drivers and receivers. XAUI's four lane architecture can provide a cheaper (through use of less expensive 2.5G optics) solution to carry this 10G data.

InfiniBand™ is a relatively new standard for interconnect between servers and peripherals. InfiniBand specifies a distributed I/O system, dealing with the connections from server-to-server and to peripherals such as storage, switches, etc. The minimum implementation of InfiniBand provides a full-duplex 250 Mbytes/sec bandwidth over 4 wires (two for transmit, two for receive) clocked at 2.5 GHz.

Implementing the XAUI and Infiniband interface standards:
The Cypress CYP32G0401DX 'Multi-Gigabit PHY' is shown as an example of a multi-channel variable frequency PHY. This is a quad-channel flexible frequency SERDES that can operate between 2.5Gbps and 3.125 Gpbs.

Figure 3: CYP32G0401DX 'Multi-Gigabit' Quad-Channel PHY architecture

The CYP32G0401DX 'Multi-Gigabit' PHY provides four-serial channels, operating from 2.5 to 3.125 Gbps. This enables support for Infiniband interfaces and 10 Gigabit Ethernet-compatible interfaces (through the XAUI interface).

Each of these four channels can operate from 2.488Gbps to 3.125Gbps and can be used in multi-gigabit serial backplane applications (electrical or optical), or at the port-side for emerging 2.5Gbps InfiniBand and 10Gb Ethernet applications.

The 'Multi-Gigabit' PHY has four modes of operation: Note: Backplanes could potentially use any mode.

Mode 1: 10-bit SERDES, Ethernet 802.3z PCS, 8B/10B ENDEC, COMMA framing
Mode 2: 10-bit SERDES, no ENDEC, no framing (InfiniBand or 802.3ae 10 Gbps Ethernet)
Mode 3: 10-bit SERDES, 8B/10B ENDEC, COMMA framing (InfiniBand or 802.3ae 10Gbps Ethernet)
Mode 4: 8-bit SERDES, no ENDEC, SONET/SDH framing (Telecom)

General PHY applications at multi-gigabit rates
A standard line card architecture is illustrated below. The section highlighted shows where high performance SERDES and programmable logic and are used to control the interface between the 'network processing engine' on the line card and the backplane. Both the HOTLink II and HOTLink III PHYs can be used to implement standard or proprietary backplanes, and the 'Frequency Agile' PSI offers the added benefit of programmability.

Backplanes are used in virtually all communication and storage systems to link line cards to a switch fabric. This architecture enables the switching of data from the port of a line card to a distant port on another card.

Figure 4: Line-card backplane applications

This ideal serial solution offers a high-performance serial interface with variable frequency operation, the option of a single or multiple channel and compliance with a broad range of standards. This can be used on both the backplane and port-side to provide flexible solutions to the designer of cutting-edge communications systems.

10GEA technology overview white paper, available from
"The once and future Ethernet" — Communications System Design, May 2001.
"Building terabit systems with multiple-gigabit multi-channel transceivers", EDN June 21, 2001.
"Switched fabric - a stitch in time" EDN April 12, 2001