To introduce the PDKs to the market, Chartered, one of the world's top three foundries, and Cadence, the world's leading supplier of electronic design products and services, will co-host a worldwide seminar series, Acceleration to Technology Access, at the following locations and dates: San Jose, May 7; Irvine, Calif., May 9; Boston, May 14; and Austin, May 16. Locations and dates for international seminars will be announced at a later time. Additional information and online registration is currently available at http://www.charteredsemi.com/PDK.htm.
The PDKs will enable Chartered and Cadence customers to immediately begin designing chips rather than first developing their own required process design kits. The PDKs provide a symbol library and technology file for the design automation flow and DRC-correct parameterized cells to automate device generation. They are validated with the Cadence Spectre(R) models in the Cadence RF/analog mixed-signal design solution, which includes AMS Designer, Composer, Analog Design Environment, Spectre/Spectre-RF, Virtuoso(R) Layout Editor and XL, Custom Placer, Custom Router, and the Assura(TM)/Diva(R) physical verification suites.