By Michael T. Moore, Cypress Semiconductor

As Complex Programmable Logic Devices (CPLDs) move into higher densities, they offer an exciting alternative for implementing complex digital designs. CPLDs offer the digital designer a level of flexibility, ease of use and fast time to market that until now has been unknown for large designs.

CPLDs provide a programmable alternative with many advantages:
•Rich logic and memory resources (480 Kbits of RAM on the Delta39K200)
•A flexible timing model with abundant routing resources
•Flexibility in changing pinout
•In-system reprogrammability
•High number of I/Os
•Integrated memory control logic, with guaranteed performance
•Availability of single chip CPLD and programmable PHY solutions

These enable fast time to market, low costs for prototyping, and the ability to add to designs or change pinouts at any stage in the design cycle.

What is the difference between
CPLDs and FPGAs?

CPLDs are available in a range of densities, scaling from the simplest logic design to the most complex that integrate logic, high-performance multiport and FIFO memory, and a SERDES for demanding communications designs. The CPLD architecture used as an example in this article is the Cypress Delta39K™ family of high-density CPLDs and Programmable Serial Interface™ (PSI™) family of programmable PHYs.

Discussion of CPLD architecture
CPLDs are coarse-grained programmable logic devices. They are generally logic-rich (that is, they have a high ratio of logic gates to registers), and have highly flexible routing resources. CPLDs are arranged as an array of clusters, linked by horizontal and vertical routing channels.

Functional building blocks of CPLDs
The most basic element in a CPLD is the macrocell (Figure 1, left). Each macrocell can implement a significant amount of combinatorial logic without the penalty of an extra pass. This is why CPLDs are considered "logic rich."

Macrocells are arranged in logic blocks (LBs), with 16 macrocells to each logic block (Figure 1, center). The macrocell performs an AND operation, followed by an OR, to implement combinatorial logic. There are eight logic blocks per cluster, all of which are connected to the same programmable interconnect matrix (Figure 1, right). Each cluster also has significant embedded single and dual port or FIFO memory.

Figure 1. Macrocell, Logic Block, and Cluster structure

What do CPLDs offer the FPGA designer?
High IO count
- One of the advantages that CPLDs offer to the FPGA designer is a greater number of I/Os for a given device density, up to 70% more in some circumstances.

Simple timing model
One of the main advantages of CPLDs over other programmable architectures is the simple and predicable timing model. This simple timing model is a result of the coarse granularity of the CPLD.

Figure 2. CPLD architecture with routing channels

Figure 2 shows the path of a combinatorial tPD (pin to pin propagation delay with one pass of logic). The ability to offer wide equations, independent of the routing in guaranteed time, is a simple formula for success. This speeds up both the initial design work and the process or debugging a design.

Benefits of the coarse-grained CPLD architecture - This coarse granularity means that paths into and out of CPLDs pass through fewer switches, and thus incur less delay. As a result, CPLDs can operate at higher frequencies than equivalent FPGAs, enabling higher performance, and are easier to route enabling faster compile time.

Benefits of the fine-grained FPGA architecture - The fine granularity of the FPGA architecture means FPGAs have fine-grained delays between each element. For implementing a small amount of logic placed close together, FPGAs are quite fast. However, as the size of a design grows, the routing delays rapidly accumulate, slowing overall performance.

Flexible pinout
The coarse granularity and predictable timing of CPLDs enables designers to change their pinouts late in the design process and retain the same timing.

Embedded memory in CPLDs
CPLDs offer abundant high-speed communications memory, with integrated FIFO and dual-port control logic for guaranteed high-speed operation. Overall this translates to higher performance for the user's design with fewer logic resources required. The integrated FIFO and dual port control control logic avoids the need for the user to create the logic manually. It also saves programmable resources that the designer would otherwise have to use.

The Cypress Delta39K offers up to 5x more memory than an equivalent size widely used FPGA: For designs requiring significant memory, a CPLD can satisfy this requirement using a lower density (and thereby cheaper) device than can an FPGA. This is a definite advantage in terms of cost and power utilization.

Why are different logic design techniques
required for CPLDs and FPGAs?

Both CPLDs and FPGAs have their strengths and weaknesses. Many designers prefer CPLDs due to the simplicity of use and high speed. CPLDs tend to be better at implementing logic-intensive functions than register intensive functions, and vice-versa for FPGAs.

Innovative packaging options for CPLDs
CPLDs are offered in a variety of densities and packages, including the single-chip self-boot solution. The self-boot solution combines the FLASH memory and the CPLD in a single package, eliminating the need for an external boot prom, reducing design complexity and saving board space.

Power use of CPLDs
CPLDs offer ultra-low standby power (A) in comparison to an equivalent size widely used FPGA (mA). CPLDs are considerably better suited to applications with a low power or temperature budget, for example handheld applications.

Many designers are familiar with traditional PLDs, and like the flexibility and ease of use offered by this architecture. CPLDs offer a powerful alternative for ASIC and FPGA designers who want a simpler easier-to-use architecture for implementing their designs. They can now extend these benefits to the several hundred thousand gate range, and achieve the high performance required for today's communications designs.

There will always be a need for ASICs and FPGAs at high (over 1/2 million) gate count designs, but below this the CPLD provides a compelling alternative.

Michael Moore is a senior applications engineer for Cypress Semiconductor. Mr. Moore wishes to acknowledge the assistance of John Wisniewski of Cypress Semiconductor in the preparation of this article.