The SDRAMS are each housed in a 219 plastic ball grid array package that saves 37% - 47% board space over a comparable discrete approaches. It also reduces I/O connections by 17% - 40% an provides lower inductance and capacitance for low noise performance. A high Tg laminate interposer provides optimum TCE match.
The SDRAMs are high speed CMOS designed to operate in 3.3 V, low power memory systems. Each chip is internally configured as a quad-bank DRAM with a synchronous interface. The devices use an internal pipelined architecture to achieve high-speed operation; the column address can be changed every clock cycle. Read and write accesses are burst oriented.
The multi-chip packages are suitable for a wide range of telecom, datacom, and embedded applications as well as high-reliability Commercial-Off-the-Shelf applications. Each is available in commercial, industrial, and military temperature ranges.