These chipsets minimize bit errors and simplify design by allowing high-jitter margin for the system interconnect. At 40 MHz operating frequency, the MAX9205 guarantees 140 ps (max.) output jitter while the MAX9206 guarantees 720 ps (min.) input jitter tolerance, allowing more than 580 ps total jitter margin for the cables or printed circuit board traces between serializer and deserializer. At this speed, the MAX9205 consumes only 34 mA, while the MAX9206 consumes only 57 mA, for a total of 300 mW total power dissipation from a single 3.3 V supply.
The MAX9206/MAX9208 deserializers transform a high-speed serial BLVDS data stream into 10-bit-wide parallel LVCMOS/LVTTL data and a parallel rate clock. A wide reference clock input frequency range (16 MHz to 40 MHz for the MAX9206, 40 MHz to 60 MHz for the MAX9208) allows the use of common clock sources, and enables data throughput up to 400Mbps for the MAX9206, and up to 600Mbps for the MAX9208. The deserializers perform automatic synchronization without requiring the serializers to send unique synchronization words or characters. This feature allows hot insertion of cards into backplanes without requiring system interruption.
The functional partitioning of these chipsets into standalone serializers and deserializers (vs. SERDES) makes them ideal for architectures employing unidirectional links. The BLVDS serializer outputs and deserializer inputs make the devices suitable for both point-to-point and multipoint topologies. For point-to-point broadcast topologies, refer to the MAX9150 low-jitter, 10-port LVDS repeater.
All devices operate over the -40°C to +85°C temperature range and are available in 28-pin SSOP packages. The MAX9205/MAX9207 serializers are pin compatible with the DS92LV1021/D92LV1023 respectively, while the MAX9206/MAX9208 deserializers are pin compatible with the DS92LV1212A/DS92LV1224 respectively.