Silicon on Sapphire has a unique ability to integrate the elements of a wireless system on a chip solution.

By John McCarthy, Peregrine Semiconductor

Rapid growth and increasing complexity of portable communications applications are forcing miniaturization of the whole system and reduction in total power consumption. The continual migration of higher performance expectations from the system into low cost implementations puts pressure on the system suppliers and by extension the component suppliers to pack more and more signal processing capability in smaller and smaller spaces with equivalent battery life and improved display functions and features. 3G is just the latest implementation of this trend. Full Internet interaction, advanced graphical user interface, multi standard phones are becoming more and more available. The signal processing required is several times that of a standard 2G phone. The radios, and there are usually several of them, must all be packed in the same physical space with the chips doing the advanced signal processing without increases in overall power dissipation.

In any complete wireless communications system there are parts of the system that are completely analog functions. These analog systems act as the interface to the outside world. RF blocks that transmit or receive the radio signals, displays, speakers, keyboards, power supplies all require significant analog processing. Most of the rest of the wireless system is digital functions to convert the signals into digital bits and then process the data to extract the usable parts for presentation to the user or the environment. Memory, DSP functions and controllers all play a part in today's high performance wireless systems.

But the problems extend beyond just the ICs. Most cell phones today, for example, have 350 - 400 components in them with less than five percent of them being ICs. The rest of the components are passive devices all of which take considerable space and drive up system manufacturing complexity and therefore cost. Many of the passive components are inductors, capacitors, and resistors that have historically escaped from the integration amalgamation by being better quality or higher precision than can be effectively integrated.

The semiconductor industry has worked long and hard to create processes that can address this need for highly integrated wireless systems. The heart of these systems today is standard CMOS technology. This provides all the signal processing, memory, and data manipulation functions needed to meet the requirements of the wireless system specs.

Technologies such as Gallium Arsenide (GaAs) provide the transmit power and some of the high performance analog processes. GaAs, however, cannot integrate digital or passive devices effectively, and therefore is limited to a few specific functional blocks which it performs quite well. BiCMOS technologies have been around for some time, and integrate analog devices with CMOS digital functions. Silicon Germanium (SiGe) has been marketed by IBM and others as the answer to the integration issue and is but the latest of these generations of complex mixed function processes. The added complexity of these merged processes requires very high mask counts to achieve the mixed device capability. SiGe typically is over 25 masks to achieve performance that is available in Silicon on Sapphire technologies with 50 percent of the process complexity. All of these semiconductor material processes fail to provide advanced high performance passive devices due to the interaction of the devices with the non-insulating substrate.

Figure 1. Silicon on Sapphire (UTSi) technology

The Ideal SOC Wireless Technology
If design engineers could define the perfect wireless technology for System on Chip solutions it would be one in which high speed devices could be manufactured that would have wide dynamic range at very low power. The desire would be to integrate complex digital functions on the same chip as memory, high performance RF functions, and high quality passive devices such as capacitors and inductors. One would want to do all this in a process that allowed high yield, low cost manufacturing which can support the huge volumes of today's wireless markets.

To make this a reality, design engineers would probably want the process to be CMOS to take advantage of the continual advancements in CMOS technology. To get the advanced RF and passive performance the ideal process would be manufactured on a perfectly insulating substrate to eliminate the substrate parasitic interaction and degradation issues.

The only process currently in high volume production that meets these requirements is Silicon on Sapphire (SOS), which was invented in the 1960's at Rockwell. Early on SOS was recognized for its high speed and low power potential. In its original embodiment, however, poor crystalline quality resulted in very low yields and therefore in high cost. Peregrine Semiconductor Corp. has developed an advanced version of this perfect wireless technology called "Ultra Thin Silicon" (UTSi®) which uses a breakthrough epi improvement process to eliminate the crystalline defects and allows standard CMOS fabrication in a very thin silicon epi layer on a perfect insulating substrate with high yields and low cost. The advantages of building CMOS transistors in the ultra thin layer of silicon over an insulating sapphire substrate include:
•Total elimination of substrate capacitance, which allows higher speed at lower power and avoids voltage dependent capacitance distortions
•Fully depleted operation, improving linearity, speed, and low voltage performance
•Excellent isolation which allows integration of multiple RF functions without crosstalk
•CMOS digital capability on the same chip as high performance RF functions
•Near ideal substrate to make integrated inductors and capacitors

For RF and high frequency mixed signal applications, the speed advantage appears in terms of high FMAX compared to Ft. FMAX measures the ability of the technology to provide power gain, while Ft is primarily a function of gate length. Bulk CMOS processes typically have FMAX roughly equal to Ft, while the SOS process has FMAX roughly 3 times Ft. This allows the designer the freedom to design at higher frequencies for a given process lithography generation or to design circuits for a given frequency in a larger geometry, lower cost technology. Comparing UTSi to standard CMOS processes the 0.5 um UTSi process has FMAX of 50 GHz which is higher than bulk CMOS at 0.25 um. An advantage from this is that the larger geometry transistors can operate with higher breakdown voltages, thereby increasing the dynamic range of the circuits which is important in RF and analog functions. UTSi at 0.25 um has the speed of the best CMOS technology today, which is 0.13 um but operates at 2.5 volts instead of the 1.2 volts of the CMOS process.

When comparing UTSi to SiGe BiCMOS, the trade offs are more complicated. The bipolar transistors in this process have very high-speed performance but they consume much higher power. None of the BiCMOS processes can integrate passives effectively thereby limiting their ability to consolidate the wireless system circuits on to an SOC solution. In general, SOS performance is in the upper speed range for a given geometry, but has significantly lower power because it is a true CMOS process.

The tradeoff of SOS versus other technologies hinges on more than just the speed and power, however. Because of the insulating properties of the substrate, multiple functions, including high quality passives can be integrated onto the chips. By utilizing a 4 um thick top metal, inductors with Qs (quality factors which are a measure of the signal losses, high Qs are needed to implement good tuned circuits) in the 40 to 50 range can be integrated on chip for frequencies up to 5 GHz. These compare to Qs of below 10 in bulk CMOS and SiGe processes. When combined with MIM capacitors that have equivalently high Qs, very high performance tuned elements, matching circuits, oscillator tanks, and transformers are possible.

Further integration of multiple active functions on single die is enabled because of the isolation provided by the sapphire substrate. Since virtually no current flows through the substrate, the dominant crosstalk terms are due to metal to metal coupling, which can be easily designed around. This allows close packed layouts of RF functions, passives, and complex digital on the same die. There are additional benefits from the digital integration on an SOS process. Not only can the designer include control and interface functions on the same chip, but he can also integrate EEPROM memory on chip with no additional process complexity. A simple crossed channel structure using a floating gate provides a low complexity, high-density non-volatile memory cell. The addition of EEPROM allows electrical programming to set bias points, center frequencies, or encode id codes or other control functions without having to include a micro-controller.


Figure 2. High IP3 mixer with integrated LO & RF Baluns.

Inductors are an essential element of any the most challenging passive component to integrate onto semiconducting silicon substrates. High Q factors are generally achieved at the expense of low self-resonant frequencies. Also, due to capacitive coupling to the substrate, the larger the inductor, the lower the self-resonant frequency and Q factor. Q greater than 10 and fsr (self resonant frequency) 3X higher than the operating frequency are desired to make good RF functions. However, with an insulating sapphire substrate both high Q factors and high fsr are possible. For example, an inductor typically used for PCS band radios is a 5 nH inductor which is readily achievable in SOS with Qs over 40.

The combination of very high linearity devices and integrated passives makes mixer functions easily done in SOS. Because there is very little capacitance to the substrate, there are no non-linear voltage dependent capacitance effect from the source and drain to the substrate. This makes very linear (as measured by IP3) mixers a reality. SOS FET mixers are literally the best in the world. UTSi Quad FET mixers are at the heart of a family of new mixer products being offered by Mini-Circuits. IP3s as high as +38 dBm are available using the UTSi core with discrete baluns. Peregrine uses a mixer core with integrated balun transformers to provide mixer ICs with unparalleled performance. Future generations will integrate these same functions into complex modulators and demodulators and integrated LO and RF amplifiers with mixers to produce tuned frequency conversions functions with world-class performance and low cost.

Another segment of the RF system where the advantages of SOS technology are clearly visible is in switching functions. Most GaAs switches require two supply voltages, and level translation to get the switching control signals on chip. SOS switches integrate the negative supply on chip and use single pin CMOS control logic to eliminate the need for level translation and a micro controller input. Next generation switches will integrate complex M × N switches on a single chip. The first product in engineering sampling phase now will do a 4 × 6 switch in a single chip. The part will replace a complex hybrid circuit currently containing 22 individual die.

Today power amplifiers are a combination of HBT power devices and many passive components and a small controller integrated onto a small hybrid circuit. One goal of the cell phone power amp suppliers is to migrate this complex product to a more integrated solution with better yield, smaller size and lower cost. Neither the silicon CMOS controller nor the GaAs HBT power device can efficiently integrate the passive networks needed to make the complete PA solution. SOS technology is able to merge 90% of the passives onto a single chip eliminating the majority of the hybrids complexity. In addition, the use of advanced flip chip packaging can attach the HBT to the UTSi passive substrate which includes the control functions and all the passive components. Discussions are underway with several PA manufacturers to develop the first of these Control Logic/Integrated Passives (CLIP) devices.

The resulting device is much easier to manufacture, at least 25 percent smaller, and has a possibility of even further integration and package consolidation. The use of advanced passive technology with integrated control logic and bump chip HBT integration makes this possible only with Silicon on Sapphire technology.

Figure 3. Control Logic/ Integrated Passives Dual Power Amp

Silicon on Sapphire has come of age, partially because the manufacturing problems that plagued it historically have been solved, but also because of its unique ability to integrate the various elements of a wireless system on chip solution. UTSi has the capability to combine high frequency performance needed to meet the needs of wireless systems at low power and low process complexity and cost. The ability to take advantage of the true insulating nature of the sapphire substrate enables the combination of complex digital functions with RF elements that need high linearity, low crosstalk, high isolation, and integrated non-volatile memory. This makes the active functions more than satisfactory to meet the needs of today's wireless systems. When high quality passives are also integrated the true Holy Grail of RF SOC is realized. Only with Peregrine's unique silicon CMOS on sapphire technology can these complex systems and passive networks be effectively integrated without compromise in performance or cost. The proof is starting to come to market with UTSi devices shipping in the millions per month today and with new products coming out at a record pace.

John McCarthy is the vice president of marketing for Peregrine Semiconductor. He can be reached at