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Microchip Technology unveiled architecture plans for its 16-bit dsPIC™ digital signal controllers. The dsPIC core is a 16-bit (data) non-pipelined modified Harvard RISC machine that combines the control advantages of a high-performance 16-bit microcontroller with the high computation speed of a fully implemented digital signal processor (DSP) to produce a tightly coupled, single-chip single-instruction stream solution for embedded systems designs. The dsPIC architecture features a full-featured DSP engine, C compiler friendly design, familiar microcontroller-like platform and easy migration of existing code for PIC18 microcontroller users.

With performance of 30 MIPS non-pipelined, the dsPIC architecture provides an ideal solution for many high-performance 16-bit microcontroller and moderate-performance DSP applications such as motor control, soft modems, automotive body computers, speech recognition, echo cancellation, and fingerprint recognition. The architecture can support up to 4 Mbytes × 24 addressable Flash program memory space and up to 32K × 16 data space. The 2.5-5.5 operating voltage appeals to many microcontroller applications that remain at 5 volts, while many DSPs are restricted to 3.3 supply voltage maximum. Devices are planned in 28-100 pin packages.

The 16-bit microcontroller features 94 instructions and 11 addressing modes. The 16 × 16-bit CPU core working registers can be used as data or address registers, and includes a dedicated register for software stack access. The instruction set comprises a mixture of flexible MCU instructions plus specialized DSP operations that execute from a single instruction stream.

All but a few instructions (including all DSP instructions) execute in a single cycle. Program branches and a few instructions execute in two cycles. The core can complete one or two (for DSP instructions) data memory reads and one data memory write per instruction cycle, using a rich set of addressing modes. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance.

A closely coupled DSP engine has been included to significantly enhance the core's arithmetic capability and throughput. It features a high speed 16-bit by 16-bit multiplier, a 40-bit adder, two 40-bit (optionally) saturating accumulators and a 40-bit bi-directional barrel shifter. Two independent address generation units (AGUs) can concurrently fetch two operands for most of the DSP class of instructions.

A novel dynamically reconfigurable data memory architecture helps maintain a microcontroller "look and feel" by allowing MCU instructions a conventional view of data space while preserving the data memory access bandwidth required by DSP operations.

The CPU core also contains other attributes often found on full-featured DSPs, including bit reversed addressing, zero overhead program looping constructs, and modulo addressing, all of which may be used by any microcontroller application code (i.e. not just DSP-based applications). In addition, the MCU instructions share other DSP resources such as address generation, multiplier and barrel shifter, increasing performance and code efficiency for many MCU functions.

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