Pentek announced a 16-channel digital receiver and A/D VIM-2 (Velocity Interface Mezzanine) module that couples FPGA technology with channelized software radio functions and represents one of the most efficient and powerful products in software radio today.

The Model 6231 is a general-purpose, 16-channel narrowband digital receiver and A/D VIM-2 module. It attaches to VIM-compatible DSP or G4 PowerPC processor boards with direct connections to two of the four processors on the baseboard. An on-board FPGA facilitates low-level preprocessing tasks, allowing the DSPs to handle the more complex, high-level chores for improved system efficiency and performance. The board is especially well-suited for high-speed synchronous data communications, wireless base stations, direction finding, satellite communications, wireless LAN, high-frequency sonar, telecom and other software radio applications. The new digital receiver module is one of over sixty off-the-shelf high-density I/O solutions from Pentek. Other compatible VIM modules include additional digital receivers, digital transmitters, A/D's, D/A's, and high-speed digital interfaces including FPDP, RACEway, and RACE++.

The Model 6231 accepts two wideband analog inputs to support direct IF bandpass sampling up to 90 MHz. It also handles baseband sampling of HF inputs up to 35 MHz using on-board anti-aliasing low pass filters. Each of the two inputs is digitized by an AD6644 or AD6645 14-bit A/D converter operating at sampling rates of 65 and 80 MHz, respectively.

The 6231 includes four 80 MHz Graychip GC4016 four-channel narrowband digital receiver chips for a total of 16 channels. Each channel delivers output bandwidths programmable from 4 kHz to 2 MHz and independent center frequency tuning from DC to 40 MHz.

Each GC4016 accepts two 14-bit parallel inputs form the four A/D converters. An internal crossbar switch provides flexible antenna allocation since all 16 receiver channels can independently select either of the two A/D inputs. A resampling filter at the output simplifies system design.

The front-panel clock and sync bus synchronizes multiple boards from a designated 6231 master. Additional sync lines allow synchronization of the local oscillator phase, frequency switching, decimating filter phase and FIFO data collection. For large systems, up to 80 6231s can be synchronized from Pentek's Model 9190 Clock and Sync Generator.

All 16 narrowband receiver outputs are delivered to a Xilinx Virtex-E FPGA with up to 600k system gates where various modes of data packing, formatting and channel selection are performed. The A/D outputs are also connected directly to the FPGAs so that wideband A/D data can be delivered directly to the processors, bypassing the digital receivers. An optional front panel connector provides 24 user-definable I/O signals to the FPGA. The FPGAs can also be configured by the user to implement custom functions.

Pentek's ReadyFlow Board Support Library is comprised of C-callable device functions that simplify board operation and setup. Some of the functions include mezzanine board control, DMA data transfers, data formatting and interrupt resource management.

Pentek provides an FPGA configuration package to be used in conjunction with the Xilinx Foundation development tool suite. Also, numerous third-party sources for IP signal processing core libraries compatible with the Virtex-E support a wide range of popular algorithms and functions.

Third-party and Pentek software development tools are available for a variety of platforms including Sun SPARCstations running SunOS or Solaris, PC's running Windows 95/NT, Digital Alphas running D-UNIX and Hewlett-Packard workstations running HP-UX.