Contemporary receiver designs rely quite heavily on the data converters that they utilize. ADCs are used to digitize the signal of interest so that the signals can be digitally processed in manners that quite simply cannot be realized in the analog domain. There is a 'cost' associated with this however; the performance demands on these converters becomes quite critical. Quite often, these ADCs are also IF sampling devices and thus additional performance demands are placed on them. The ADC is relied upon to faithfully and accurately digitize the signal of interest.

There are many sources of error within an ADC. Historically data converters performance was limited by their slew rate performance. However, improvements over the last few years removed slew rate as a limiting factor in data converters. Today's converters are more limited by DNL errors than perhaps any other defect. Not only do DNL errors effect the usual parameters such as SNR and SFDR, but they can also have a big impact on converter gain, especially at lower signal levels. This can be especially important in communications channels such as GSM and CDMA where power estimation is vital to proper operations of the wireless network.

DNL errors are caused when the transfer function of the ADC deviated from the nominal on a code by code basis. Each code size of an ADC should be exactly the same width. When they are all stacked up, the complete range of the converter is constructed. However, defects in resistors, capacitors and transistor geometries as well as numerous other effects can cause the steps of the ADC to deviate from the nominal size. These errors are called DNL errors. Historically, DNL errors have been associated with static performance of data converters. Such characteristics as code widths and step sizes are common terms applied to normal characteristics. However, in the frequency domain, they can contribute to characteristics such as increased noise, distortion and erroneous signal levels.

*Figure 1*

If DNL error occur in clusters, then the integral linearity (INL) of the converter can be sacrificed as shown. INL errors cause increased harmonic distortion, within the ADC, even at the lowest analog frequencies. Therefore, great care must be taken to keep the DNL errors from clustering and to minimize overall INL.

However, even if the effects of INL have been minimized, there will still exist some residual DNL errors. These errors will often find themselves at the most undesirable locations. One such place is at mid-scale of the converter. When large signals are present on the ADC input, there are not too many problems as codes near mid-scale occur infrequently. However, as the input level falls, the probability that codes near mid-scale will occur increases significantly as demonstrated in equation 1.

P(V_{sin e}) = 1

πsquare root A_{2} - V_{2}

Equation 1

where; V is the input voltage (or equivalent ADC code value) and A is the full-scale range of the ADC (A can also be expressed in ADC code value).

Looking first at the increase in noise floor, consider the following analysis. In a converter with ideal step sizes, the rms value of the DNL error should be .289 (*q*/square root12) lsbs. For a 14 bit converter, this corresponds to an SNR of about 86 dB. However, if a code is missing near mid-scale, the DNL error is increased by a factor of two to .579 lsb (at the missing code) producing a small signal SNR of 80 dB (referenced to full-scale). This stands to reason since to a converter with a very small input signal, a missing code can look like a converter with a missing bit (the lsb), especially if only 2 or 3 converter codes are being stimulated by the input signal. Thus, a missing code can result in the loss of up to 6 dB of SNR (again referenced to full-scale) at small signal levels.

*Figure 2*

Yet another class of issues with DNL exists. These are errors in gain for low level signals. The visualization of this is simple. In Figure 2, the left drawing shows a converter with nominal step sizes (ideal DNL). When stimulated by the sine input below, one of two levels is produced at the output. In viewing the graph on the right, notice the 2 short codes in the middle of the scale. For the same input signal level, 4 output levels occur. Although the input signal is the same, the digital output codes now have twice the range. When evaluated by numerical techniques, an apparent gain of two occurs (or 6 dB). The size of the gain error would depend on the type of DNL error causing the problem.

This simple illustration shows how DNL can effect signal gain. However, whether it is an issue or not depends on where the DNL errors occur. One of the worst locations for this type of DNL errors is right at mid-scale. Figure 3 shows how the gain error appears for an input power level sweep. With the error at mid-scale, as the input level is swept from largest to smallest, the signal becomes centered on the DNL errors. As the signal gets smaller and focuses on the short codes, the apparent gain of the converter increases. Thus the problem is aggravated as the signal levels are reduced.

The data presented here is based on a simulated converter with two -.75 LSB errors side by side (2 'short' codes). The remainder of the converter codes are ideal.

With the errors at mid-scale, the gain error gets progressively worse until the noise floor of the converter is reached. This is shown in Figure 3 as the mid-scale trace. In this graph, the horizontal axis is input signal level below full-scale and the vertical axis is the gain error in dB. With the two short codes, the gain of the converter increases as the input level is reduced. Since these are short codes as in the form of Figure 2, the gain is positive. It is just as possible that the codes could instead be long, and the gain error would be negative.

Also shown in Figure 3 are the gain errors associated with the DNL errors being 5 and 2 codes offset from mid-scale. With the DNL errors offset from mid-scale slightly different scenario develops. Under this condition, as the signal levels are reduced, the gain errors begin to mount. However, at some point, the short codes are no longer exercised due to their offset and once again the converter gain error is reduced to zero. The error begins to occur, but rapidly disappear as the problem codes are no longer exercised once the input signal is below a certain signal level. For comparison, Figure 3 also shows the gain error of a device with ideal DNL. Notice there are no errors until the noise of the converter causes computational errors.

*Figure 3*

**Conclusion**

Since this problem is caused by DNL errors, it can be remedied through the addition of dither (see Analog Devices' AN-410). The problem can also be avoided by simply having enough gain prior to the ADC to prevent the desired signal from ever falling to these levels. Likewise, if the noise from the front end of the receiver is 5 to 10 dB above the quantization noise, thermal noise will swamp out these problems and act as dither to clean up the problem.

While this data is based on a simulated 12 bit converter, the problem can be viewed in the lab under very 'quiet' setups. It should also be remembered that in many wide input bandwidth converters, thermal noise within the converter dominates quantization noise already. Therefore, in these converters, this phenomenon will not present any problems. This DNL anomaly can only be observed in ADCs (or systems) with noise levels less than an LSB.