Aitech Defense Systems Inc now offers the high performance SP0, a space-qualified, radiation-tolerant 3U CompactPCI SBC with an exceptionally low power of only 10 W for manned spacecraft and unmanned satellite subsystems and platforms.
The compact MPC8548E, PowerQUICC-III PowerPC-based SBC provides high levels of on-board functionality and integration combined with low power dissipation. It can achieve a processing speed of 1.17 GHz and 333.3 MHz of core complex bus (CCB) and DDR-1 memory speeds, while adhering to the low power and small form factor requirements necessary in most satellite and spacecraft, mission-critical applications.
The SP0's processor includes an e500 System-on-Chip (SoC) integrating both an L1 cache with 32 KB instruction and 32 KB data and a 512 KB L2 cache. A large user Flash of 1 GB is standard, with the option to expand up to 8 GB.
Supporting both processor and application needs, the large on-board memory also includes up to 512 MB of fast DDR1 SDRAM with ECC protection for high data integrity as well as 512 KB of redundant Boot Flash.
This compact board's extensive I/O, all of which is routed to the rear panel connectors for application usage, reduces the number of additional peripheral cards needed for a fully functional subsystem. Pushing the limits of on-board functionality and I/O interfaces, the SP0 includes two Gigabit Ethernet ports, four asynchronous, high-speed serial communications ports and up to five general purpose discrete I/O channels - and more.
An included industry-standard PMC slot, either air- or conduction-cooled, accommodates additional modules and on-board functionality. In addition, up to eight PCI Express lanes or four Serial RapidIO lanes as well as dual PCI buses further help increase on-board high performance and exceptional functionality.
When operating as a system controller, instead of as a peripheral card, the new SP0 supports up to seven additional cards on the PCI backplane complete with clock signals and interrupt and arbitration support.
Three watchdog timers on the SP0 offer exceptional system safety parameters and reliability. One watch dog timer, located within the SoC processor, generates an internal CPU interrupt to alert the application of a pending fault. After the first timer expires and then the second timer expires, a non-maskable hardware reset is performed, which also resets the entire board. Located in the on-board FPGA, the third timer can reset the whole board or only certain I/O devices after the expiration period.
A 1 PPS (pulse per second) timer provides a critical system backplane and external heartbeat for synchronization to other autonomous computing and communications subsystems on the satellite bus or spacecraft platform.
For more information please visit http://www.rugged.com/sp0 .
August 13, 2012