Wireless Design and Development
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Home > Diagnosis Technology Slashes Debug Effort for Complex SystemVerilog Assertions

Diagnosis Technology Slashes Debug Effort for Complex SystemVerilog Assertions

OneSpin Solutions has mainstreamed comprehensive formal assertion-based verification (ABV) for SoC, ASIC and FPGA designs by delivering a structured, step-by-step approach to its use and adoption. This approach is enabled by five interoperable products in a new, integrated 360® MV product family designed for formal verification novices, experienced users, and experts. Entry and exit points at six application levels let companies best meet their verification needs. OneSpin also announced a new proof-based debugger for complex SystemVerilog Assertions (SVAs). The debugger automatically locates the root-cause that makes an assertion fail, addressing a critical productivity issue in the use of complex assertions. It complements simulation-based verification and requires up to 5X less verification effort than thorough module/subsystem testbenches.

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http://www.wirelessdesignmag.com/product-releases/2009/02/diagnosis-technology-slashes-debug-effort-complex-systemverilog-assertions
Summary: 
OneSpin Solutions has mainstreamed comprehensive formal assertion-based verification (ABV) for SoC, ASIC and FPGA designs by delivering a structured, step-by-step approach to its use and adoption. This approach is enabled by five interoperable products in a new, integrated 360® MV product family designed for formal verification novices, experienced users, and experts....
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Source URL: https://www.wirelessdesignmag.com/product-releases/2009/02/diagnosis-technology-slashes-debug-effort-complex-systemverilog-assertions

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[1] https://www.wirelessdesignmag.com/content-item-types/product-announcement