A new architecture for video serializers and deserializers, built specifically for mobile devices, can address the demands for increasingly graphics-rich visual content.
The emergence of the “personal information device” driven by rapid adoption of cell phones and their expanding panoply of features, capabilities and services is pushing the need for high resolution displays capable of displaying the increasingly rich video content. Video messaging, still photos, and desktop-style user interfaces with touch screen operation require both larger displays in terms of horizontal and vertical pixel densities, as well as the ability to render a higher number of colors per pixel. While yesterday’s cell phone may have touted a 16-bit color QCIF display, tomorrow’s converged device will not just have mobile phone capability, but multimedia, computing, navigation and numerous connectivity features such as Bluetooth, Wireless LAN, Near Field Communication, and may well present all this capability using 18- to 24-bit color VGA resolutions (640 × 480 pixels).
To illustrate these examples, this raises the necessary bandwidth capability to the display from around 400 Kbits per displayed frame (176 × 144 × 16) in the QCIF case to roughly 7.4 Mbit per frame in the case of VGA (640 × 480 × 24). At frame refresh rates of 50 frames per second, we are migrating from a 20 Mbit/sec data transfer rate in the first example, to data rates exceeding 360 Mbit/sec in the second example ignoring any display overhead (blanking) or overhead in the data transmission. Higher resolutions, higher frame refresh rates (for full motion video, 60 Hz is common) and overhead in both display and data transmission easily push practical bandwidth requirements into the range above 1 Gb/s.
VBR = Frefresh× (H × V × Dcolor× 3 ) × (100% + OH) [bits per second]
Where: VBR = Video bit rate, in bits per second Frefresh = Frame refresh rate, in frames per second (or Hz) H = Horizontal number of pixels V = Vertical number of pixels Dcolor = Number of bits per color (Red, Green or Blue) OH = Gross display and transmission overhead in percent.
Legacy solutions may employ either fully parallel solutions (one wire for each bit weight transmitted) or asynchronous serial buses such as SPI to transfer video data. However, when going from 16- to 24-bit per pixel of video, simply extending the width of the parallel bus is hugely impractical simply for space reasons, especially if the video signal needs to be routed through a hinge, swivel, pivot or slider type of mechanical display connection. Also, the increase in signal frequency will only exacerbate emitted radiation through the use of single-ended CMOS type signaling, due to its characteristics of full voltage swing and asymmetrical signal-ground return topology. Instead of aggravating the problem by increasing signaling rates and wire count simultaneously, vendors want their EMI cost of ownership to go significantly down, not up.
Serializing the interface to the display seems a natural solution, by solving at the same time both the space constraint problem (by reducing the amount of wires) and the EMI
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Table 1. Overview of required (serial) data bandwidth as a function of example display sizes.
New consortiums like MIPI (Mobile Industry Processor Interface) have been working for the past few years to standardize such serial links for the cellular handset and similar markets. Such standardization brings the benefit of through industry collaboration, being able to cover a wide range of current and future technical requirements, interoperability between devices, and ubiquity of product solutions.
However, there will be an initial timeframe where fully-integrated MIPI-based solutions are not yet available, and there will be niche applications where integration into an ASIC is economically not an option. In these cases, low power and standalone serializer-deserializer solutions that are thoughtfully designed to mitigate space and power concerns, can earn back their cost by greatly reducing the complexity, design effort, and time to market of high-resolution video designs.
This article will briefly introduce serial interfaces in the context of mobile display applications, discuss how serial solutions address the various application trends and technical requirements and introduce example IC solutions including a new serial interface architecture developed by NXP Semiconductors specifically for mobile devices. In addition, we will give an overview of where MIPI stands today, where it is headed and the potential for our customers to migrate to MIPI-based solutions in the future.
High-speed Serial Interfaces for Mobile DevicesHigh-speed serial interfaces replace parallel topologies in a wide array of applications today. Many of today’s common interconnect standards such as USB and PCI Express are based on serial transmission to achieve speed, physical compactness and link robustness, as do a vast array of implementations less visible to the consumer, such as notebook computer display interconnect, high-speed backplane interconnects, and emerging memory bus architectures.
Though different in scope and optimized for best performance in specific environments, high-speed serial interconnects all make use of a few essential elements. Perhaps foremost, several important benefits are all at once achieved by using differential signaling, which provides a substantial reduction in noise emission and allows the signal swing to be substantially reduced, in turn reducing the amount of required signal power.
The ratio at which data is serialized is chosen such that per parallel word transmitted, all data bits (the “payload”) plus any overhead (due to line coding more on this later and the addition of other useful bits such as parity or error correcting code) can be transferred within the parallel clock period. For example, to serially transmit one 24-bit video pixel (8-bits each for R, G and B color words) along with its synchronization bits (horizontal sync, vertical sync and data enable) without any other overhead, one would need the outgoing serial bit rate to be at least 27 times the incoming pixel clock rate. Let us assume that two additional general purpose bits will be added, as well as one parity bit (again, more later) to complete a total serial bit count of 30 bits per period of the parallel pixel clock.
The frequency at which video data will be transmitted is bound to two basic quantities: the physical implementation of the video display grid (number of horizontal and vertical pixels), and the display refresh rate (the rate at which the entire display’s grid of pixels and lines is refreshed once). Since the display and display driver need additional time between lines and between the end and start of a frame (also known as horizontal and vertical back and front porches, respectively) again some overhead is allowed for here. Ultimately, the pixel rate can be calculated by multiplying the display refresh rate by the number of horizontal and vertical pixels including overhead. The required serial bit rate can then be calculated by multiplying the pixel clock frequency by the number of serial bits per frame (see Table 1).
Should display sizes cause the serial bit rate to exceed what is desirable from an IC implementation or application standpoint (e.g. one might wish to limit the serial interface’s signaling rate to typical LVDS maximum rates of 650 Mbps so that it can be realized in cheap and generic CMOS processes), then it is possible simply to distribute the payload over multiple serial lanes, reducing the absolute signaling rate per lane by that same factor. This makes it possible to scale from lower end display sizes such as QVGA (bitrates of about 120 Mb/s) all the way up to high-end display sizes such as XGA (bitrates of around 1250 Mb/s) simply by utilizing the necessary number of lanes as needed (see Table 1 for example bit rate calculations).
Depending on the specific end application for the video serial interface, additional overhead may or may not be needed, at the expense of complexity and efficiency. For traversing relatively short distances (several or tens of centimeters), the simplest solution is source-synchronous transmission, where the clock reference for the serial data is transmitted as a separate signal along with the data. When longer distances have to be reached (several meters), the difficulty of controlling skew, jitter and other timing issues will increase to the point where it is necessary to use line coding, a process in which the clock reference is embedded into the data stream. This in turn necessitates clock recovery from the data stream at the receiver end, also increasing complexity and inefficiency depending on the level of sophistication of the line coding scheme. Further complexity may be needed when it is necessary to encrypt data for intellectual property protection reasons. But for the purposes of this article, links usually remain short and internal to the mobile device. Moreover, any overhead added to the original data effectively increases the amount of power required to transport each bit, a consideration of paramount importance in battery powered handheld devices second to, most likely, space constraints. For these reasons, the arguments are strong to opt for simple source-synchronous transmission as suitable and appropriate for the intended application space.
About the Author
Nic Roozeboom is technical marketing manager, High-Speed Interface, Product Line Interface Products, BL Standard ICs, for NXP Semiconductors.