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Figure 1. The typical digital filter design process.
One way to compensate for these and other high-level issues is to simplify the design process by using common software tools for multiple tasks. Doing so can facilitate code reuse across these tasks, but more importantly, it can foster collaboration by allowing different groups to more easily understand and utilize the work of the others.
The Digital Filter Design Toolkit (DFDT) Version 7.5 is a software add-on for the LabVIEW graphical development environment. As a design tool that is integrated into a general purpose development environment, the DFDT facilitates both interactive and automated design that can be incorporated into aspects of the design process: from initial specification, design, to implementation.
Facilitating the Design Process
Digital filter design typically follows the design flow shown in Figure 1. The process starts with specification of desired filter attributes. To interactively specify and design a filter, the toolkit includes tools for classical filter designs and design through placement of poles and zeros. As engineers modify parameters, the interface immediately shows the magnitude response and pole/zero locations on the Z-plane based on your selections. The pole-zero design tool (Figure 2) allows click-and-drag placement of poles and zeros on the Z-plane.
Engineers also can programmatically design these and other filter types with included Virtual Instruments (VIs). VIs are the subroutines of the LabVIEW graphical programming language that allow engineers to easily wire into custom applications.
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Figure 2. One of the interactive design panels allows users to specify a filter design by positioning poles and zeros by dragging and dropping them using the mouse.
To analyze the design, the toolkit provides VIs to plot frequency response, pole/zero locations, group delay, phase delay, impulse response, and step response. It also installs a set of "process-signal" VIs that allow engineers to further evaluate the potential design by applying it to a signal. Designers can easily access live, simulated, and previously acquired signals. To implement a filter, simply wire the design and signal into an appropriate process signal VI from the toolkit.
If the engineer is planning to deploy a floating-point design, they can export the results of the design as a set of floating-point filter coefficients. They also can deploy it using the process signal VIs within a custom LabVIEW application.
Although floating-point designs might be complete at this point, fixed-point design continues with modeling of quantization effects. This job involves specifying how the floating-point design will be converted to a fixed-point implementation. Engineers start by assigning a filter structure, selecting from the 23 possibilities supplied with the toolkit; these range from the Direct Form and Cascaded Form to Lattice AR (Auto-Regressive), Lattice MA (Moving Average), and Lattice ARMA (Auto-Regressive and Moving Average).
After selecting a structure, the engineer can specify how the model will represent the filter coefficients and how it will handle overflow and rounding. The toolkit provides tools that use these constraints to quantize the floating-point coefficients and simulate the application of the filter.
The next step is to analyze and validate the fixed-point filter. The engineer can examine any of the same set of plots that were available for the floating point design here, with the fixed-point result superimposed for easy comparison. They also can examine an available quantization report that shows the floating-point coefficients and the quantized fixed-point coefficients side-by-side with counts of the number of zeroed/saturated values. An available simulation report shows min. and max. values for the operations associated with applying the filter.
Deploy the Design
Based on these results, the engineer can decide whether to revisit the design until it meets his specifications. Alternatively, he can proceed with implementing his design. To this end, the toolkit includes automatic code generation capability that can create code types that include ANSI-C, integer LabVIEW, and LabVIEW/FPGA. The latter can be deployed with the LabVIEW/FPGA module, allowing the designer to embed the code in an FPGA.