Capturing the promise of Bluetooth in hardware requires a high level of integration.By John Notor, Tality
Bluetooth wireless networking technology continues to stimulate the imagination of the wireless industry as a low cost, low power, and small footprint networking solution which can replace wired connections to consumer devices. Capturing the promise of Bluetooth in hardware requires a high level of integration, ideally including the wireless transceiver, the baseband processing, and the MAC in a single chip solution. The only existing technology with any hope of accomplishing this is CMOS.
The advantages of CMOS lie not so much in the wonders of its analog and RF capability, which, on their best day are just okay, but on it's digital capability. CMOS technology, including support tools and years of stable foundry infrastructure, is the cutting edge digital process in terms of scale, speed and cost. The fact that adequate RF and analog circuits can be implemented in CMOS means that it is the best mixed signal technology in terms of circuit diversity, complexity and cost available today.
The Bluetooth Paradigm
Bluetooth is a wireless networking system developed by the Bluetooth Special Interest Group to enable standardized short-range wireless networking between voice and data equipment. The currently released standard, v1.1, available for free download on the Bluetooth SIG website, http:\\www.bluetooth.com, supports a raw data rate of 1 Mbps, and a maximum burst rate in one direction (DH5, 5 time slots) of 723.1 kbps.
The radio air interface uses Time Division Duplex (TDD), Frequency Hopping Spread Spectrum (FHSS), and Time Division Multiple Access (TDMA) technologies operating in the 2.4 GHz Industrial, Scientific and Medical ISM band. Channel spacing is 1 MHz, and 79 channels are assigned starting at 2402 MHz and continuing to 2480 MHz on 1 MHz centers. Time slots are 625 us wide, generally alternating between transmit and receive. Packets may occupy 1, 3, or 5 continuous slots at a single transmit frequency before hopping to the next frequency for a receive acknowledgment.
The modulation selected for Bluetooth is binary Gaussian Frequency Shift Keying (GFSK) with a nominal peak deviation of 157.5 kHz. The premodulation Gaussian pulse shaping is specified as BT = 0.5, or, in other words, the 1 Mbps data stream is filtered by the equivalent of a 500 kHz nominal bandwidth Gaussian filter.
Bluetooth networks are ad hoc, meaning that Bluetooth networks function on an as needed basis, rather than a permanent basis like familiar wired networks. So, in a Bluetooth network, the network members may come and go with time, networks may reassemble themselves on the fly, and network control may pass from one node to the next depending on the circumstances. The core organizing unit of a Bluetooth network is a piconet, which contains up to 8 active devices, one master unit and up to seven slave units. Groups of piconets, called scatternets are envisioned by the specification, in which piconets share one or more devices in common.
Bluetooth is intended to operate over relatively short ranges using three power classes: Class 1 (+20 dBm maximum power, limit of range about 100 m), Class 2 (+4 dBm maximum power, limit of range about 20 m), and Class 3 (0 dBm maximum power, limit of range about 10 m).
The Bluetooth specification balances the desire for range implied by transmitter power and receiver sensitivity with the necessity of operating with co-channel and adjacent channel interferers, either from other Bluetooth networks or other occupants of the 2.4 GHz ISM band. These include other networks (IEEE 802.11, HomeRF, etc.) and other ISM devices like microwave ovens.
Bluetooth modules are intended to be low cost, power efficient devices that meet modest environmental and link quality requirements to support ad hoc networks.
Bluetooth Receiver Requirements
Figure 1 shows a typical implementation of a Bluetooth transceiver. The receiver, which is the focus of this article, is implemented using a single conversion low intermediate frequency (IF) architecture. The low IF architecture has a number of advantages:
A single synthesizer means less operating current
An IF limiter, with its ability to handle a wide signal dynamic range virtually instantaneously, eliminates the need for AGC
A low IF means the channel filter and the demodulator can be implemented completely on-chip
Table 1 summarizes the Bluetooth module requirements, reflects those requirements to the input of the RFIC for a typical design, and lists typical performance for the standard Tality LP implementation. Note that the assumed insertion loss between the module antenna output and the RFIC receiver input is 3 dB.
Minimum RF Performance for Bluetooth
In order to give some perspective to the design problem for a Bluetooth receiver, let's examine the performance required to meet two commonly specified and well understood specifications: sensitivity and intermodulation level. With a little quick arithmetic, we arrive at the conclusion that the RFIC needs to have a minimum noise figure of 24 dB, and a minimum input third order intercept point (IIP3) greater than -25.5 dBm.
No one would actually design a Bluetooth RFIC to meet the minimum requirements, but this analysis serves to illustrate a couple of points:
Bluetooth requirements are a balance between sensitivity and distortion for a relatively short range link
It does not take a state of the art analog process to meet basic Bluetooth specifications in an RFIC design
Figure 1. Simplified Bluetooth Receiver Block Diagram
Moving to the next level of detail, Table 2 shows one version of subcircuit performance for the stages prior to the limiter (see Figure 1) which, when combined, just support the overall RFIC performance with respect to noise figure and IIP3. Here again, it is clear that the individual stage performance does not have to be wonderful to meet the minimal Bluetooth requirements. For instance, a typical 18 dB CMOS LNA at 2.4 GHz can be expected to achieve a noise figure well under 10 dB, and an output IIP3 better than +5 dBm.
Serial Data Recovery
A Bluetooth link requires circuitry necessary to take a serial data stream, convert it to a 2GFSK wireless modulation, transmit the modulated signal wirelessly, receive the signal, demodulate the received signal and recover the serial data stream. This is minimum functionality that must be built into the transceiver function.
So, where should the data be converted from an analog signal which is the demodulated form of the 2GFSK modulation to standard digital format and how should that be done? This conversion process is sometimes called data slicing.
Many Bluetooth implementations use an analog slicing technique composed of a comparator circuit and an appropriately determined threshold. Detected signal levels above the threshold are converted to digital logic 1 levels, detected signals below threshold are converted to digital logic 0 levels. This approach seems simple enough, but the question arises: "How is the threshold level determined?"
The Bluetooth specification allows a fair amount of transmitter frequency drift during packet transmittal, up to +40 kHz for a 3 or 5 slot packet, plus an initial transmit frequency error of +75 kHz. So, that's a net frequency error of +115 kHz worst case. Since the peak deviation is 157.5 kHz, that means that the peak to peak frequency error is 73% of the modulation peak to peak amplitude.
If a fixed voltage threshold were used to slice the data, significant signal to noise ratio would be lost due to frequency drift as the signal center frequency drifted around over a 1 to 5 packet time period, and the result would be unacceptable BER performance. So, some means has to be found to correct for static and dynamic frequency errors.
The standard analog technique is to use an RC time constant to filter the demodulated data and recover a DC threshold level. In some cases, a single time constant is used, in other cases a dual time constant is used. In the dual time constant case, a short time constant is selected for a kind of fast initial DC level acquisition during paging or immediately after a frequency hop, followed by a long time constant when the receiver expects multiple data packets with no frequency change.
Another approach is to digitize the data with an analog to digital converter (ADC) and use digital signal processing techniques to recover, track the DC level, and slice the data. At the expense of some additional current for the ADC, this approach brings all the benefits of temperature and process insensitive digital data acquisition to bear on the problem of data slicing. Because this is the most robust approach to data slicing, Figure 1 includes an ADC. CMOS is the industry standard process for implementing low cost, low current ADC's, so including the ADC in the RFIC is an obvious choice.
The Bluetooth concept puts a premium on power management, since Bluetooth targets portable applications as a core part of the networking implementation. The Bluetooth specification identifies four power management modes: Active, Sniff, Hold, and Park.
In Active mode, the device plays an active role in a piconet, and is an active listener when in slave mode. So the device draws current even if it is not being addressed directly while in receive mode.
In Sniff and Hold modes, the device listens occasionally, based on an agreement between the master and slave units about the timing. As a result, in these modes the device can turn off a large part of it's own circuitry to conserve current, perhaps running just the timer circuitry necessary to create a device wakeup when required.
In Park mode, the device removes itself from active membership in the piconet and powers down. The device wakes up periodically to check for broadcast messages, which can bring it back into active status on a piconet.
To support these modes and to minimize current drain in active mode, the RFIC design must allow independent control of the current consumption of subcircuit blocks. In general, the RFIC needs to implement three operational modes: receive mode, transmit mode and sleep mode. In receive mode, only the circuits required for signal reception are actively drawing current. All transmit only circuitry is turned off. Similarly, in transmit mode, all of the receiver only circuits are powered down. In sleep mode, the entire RFIC is placed in a minimum current drain condition.
In addition to being able to power down these circuits, the RFIC must be capable of powering up quickly, especially in moving from transmit to receive and back during a lengthy exchange of data between a master and a slave. Because CMOS logic circuit draw relatively little quiescent current, and CMOS switches require low drive currents to maintain either an OFF or an ON state, creating low power modes with quick recovery times is relatively straightforward. In addition, CMOS control logic can remain fully active and yet draw only microamperes, minimizing the digital delay required to activate a device.
The Cost of Doing Business
Production cost is always a major component of the decision making process when it comes to RFIC development. Bluetooth is a consumer market technology which demands the lowest cost implementation available.
CMOS has been and continues to be the lowest cost mixed signal process available. For the sake of comparison, Table 3 shows the approximate relative cost for CMOS, BiCMOS and SiGe BiCMOS processes for an 18 sq. mm die. To create Table 3, $0.10/sq mm has been arbitrarily set as the CMOS production cost metric and calculated the relative costs of BiCMOS and and SiGe BiCMOS dies for purposes of comparison. Industry standard numbers will vary with process and foundry.
John Notor is a system architect at Tality. He can be reached at (408) 473-8373 or by email at firstname.lastname@example.org.