Ask engineers what they need in a wireless memory and often the answer is low cost followed by low power and high performance. DRAM technology is finding widespread acceptance in wireless applications because it offers low cost and high performance. Memory suppliers like Micron Technology, Inc. are working on new technologies to expand the use of DRAMs in wireless applications.
The past few years have seen an explosion in the demand for wireless handsets. The venerable cellular phone is rapidly evolving into a multi-purpose communication center. Even less sophisticated cell phones now have the ability to receive caller ID, e-mail and voice messages. With newer technologies promising increased data bandwidth, added functionality seems unbounded. Web browsing, MP3 capability, streaming video and PDA functionality all seem destined to be standard features in the immediate future.
To support increased processing requirements for these new features, handsets must significantly increase the amount of on-board processing power. Processor and DSP components are more sophisticated and the supporting memories are forced to keep pace with the increased throughput. Density requirements and read/write bandwidth issues are more significant factors in the memory subsystem design. Low power consumption is still a critical factor when choosing memory technology, but there are significant density and bandwidth tradeoffs to consider. This article will focus on issues affecting low-power memory operation and how DRAM technology plays an increasing role in the wireless handset marketplace.
A critical design constraint on all portable products is battery life. There is an endless struggle to improve handset features without impacting the time between battery charges. Battery technology improvements have resulted in significant capacity increases for a chosen system weight and volume. Semiconductor manufacturers are constantly attempting to reduce power consumption while maintaining or increasing performance.
One way to quantify this issue is to look at memory usage models for a generic wireless handset (Figure 1). The idle and active periods occur when a handset performs a function and memory is accessed. Note the largest portion of time is spent in the sleep state. The sleep state includes periods where the system is waiting for an interrupt and there is little or no need for significant amounts of RAM storage. Significant amounts of current are required during this standby period to refresh a DRAM memory array. As will be shown, memory manufacturers are focusing on several clever means of minimizing standby current consumption requirements.
Low-power memory devices reduce the VDD core and I/O voltages to reduce total power consumption. Standard core voltages for Flash and SRAM technologies have migrated to 1.8 volts and DRAMs to 2.5 volts. I/Os for Flash, SRAM and DRAM operate with a 1.8 V rail. It is only a matter of time before there is a unified 1.8 V power supply standard for the entire memory subsystem.
Power Savings Due to
Wireless applications with traditional asynchronous memory are giving way to devices with high-speed page or burst modes. These newer products take advantage of accessing adjacent addresses from a memory device at a much higher rate than does random access. The initial access for a burst mode memory takes the same amount of time as an asynchronous device, but subsequent addresses can be read at a much higher rate. This mode of operation is most effective when the host processor fills a cache line. Migrating from asynchronous to synchronous architectures allows for significant savings in power consumption. Both the high-speed transfer rate and the more orderly synchronous access result in reductions in power consumption.
Due to high-speed burst operations, the active period of a synchronous device is shorter than that of an asynchronous device. A typical 100 MHz SDRAM can burst 8 addresses in 130 ns. A 60 ns period is required to access the initial address and then each subsequent address requires an additional 10 ns (see Figure 2). On the other hand, a 60 ns asynchronous SRAM device requires 480 ns to access 8 words. The dramatic time reduction during a read burst offsets the higher active currents on high-speed synchronous devices.
In a traditional asynchronous memory, the device must wait for all address lines to settle before the chosen address is successfully accessed. As long as the address lines are unstable, there are large amounts of current used to bias different rows within the memory array. With a synchronous device, all addresses are transferred to the internal row and column decoders coincident with the clock's edge. This simultaneous transfer eliminates the extra current consumed during the address settling time on asynchronous devices.
I/O Characteristics Effecting
A not so obvious place to reduce power consumption is the system data bus. The energy required to operate the bus is described in the equation E = 0.5*C*(V**2)*f*n*t. E - the energy consumed during a read burst
C - the capacitance of a single PCB trace
V - the supply voltage level used for the data bus
f - the bus frequency or data transfer rate
n - the number of data lines transitioning from low to high during a read cycle
t - the time taken during the read burst
The frequency, time, and transition count offer little opportunity to reduce total power dissipation. If either the time or frequency variables are decreased, the other variable must be increased to maintain the same data bandwidth. It is assumed only half the data lines will transition from one read cycle to the next and half of those transitions will be low to high. Only low to high transitions draw current.
Things get interesting when the remaining V and C terms are considered. Reduction in bus capacitance is possible when controllers implement an independent memory bus. An independent bussing structure reduces data bus trace and I/O pin capacitance by providing an isolated bus for the memory subsystem and a second bus to support peripheral I/O functions. Processor memory interfaces will increasingly leverage the advantages of an isolated bus, thus increasing performance and simultaneously decreasing power consumption.
The squared voltage term in our energy equation is where the real savings are possible. Reducing bus I/O voltages can significantly decrease energy consumed during a data transfer. Changing from a 3.3 V rail to a 1.8 V rail results in energy savings of over 70 percent. This energy savings is one reason why many processor and memory manufacturers are implementing separate supplies for the core and I/O voltages. DRAM technology can operate at a core voltage of 2.5 volts but can also operate the I/O pins at the 1.8 volt standard for low-power memory devices.
Figure 3 demonstrates the savings possible when a low-voltage isolated memory bus is implemented. The calculation assumes a 16 bit bus with only 8 bits (on average) transitioning during each read cycle. Of the 8 transitioning bits, half (4) transition from low to high. Only a low to high transition draws current from the supply, and half the transitions are low to high. The isolated bus calculation demonstrates the effect of a bus capacitance reduction down to 15 pf, a VDDQ reduction to the 1.8 V level, and the use of high-speed synchronous memory. The isolated bus uses a synchronous memory and the unified bus assumes an asynchronous memory architecture. The savings are in excess of 85% with the isolated architecture providing not only a significant reduction in energy consumption, but also a dramatic improvement in read bandwidth.
Energy (isolated, low voltage) = 0.5*15 pf * (1.8 V * 1.8 V) * 100 MHz * 4transitions * 80 ns = 0.78 nJ
Energy (unified, standard voltage) = 0.5*30 pf * (3.3 V * 3.3 V) * 16.7 MHz * 4transitions * 480 ns = 5.24 nJ
Figure 3 Example of the energy savings with standard vs. low voltage bus structures
DRAM For Wireless Applications
With the increased processing requirements of next generation handsets, the higher densities offered by SDRAM devices becomes increasingly attractive. DRAM has suffered in this market due to the relatively high standby currents of the required refresh operation. Next generation SDRAM devices targeting portable applications reduce standby power consumption by altering the way refresh is performed.
These low-power SDRAM products include the following features:
Temperature Compensated Self Refresh
Partial Array Refresh
ה.5 V VDD, 1.8 V VDDQ
Chip Scale FBGA Packaging
Industry Supported JEDEC Standard
The first reduction in current consumption occurs when you modify the refresh rate depending on the ambient temperature. At extreme temperatures DRAM devices need to be refreshed more often to maintain data integrity. If a handset is operated at moderate temperatures, a DRAM can be refreshed less frequently, resulting in lower standby currents. The handset must include an on-board temperature sensor to decide the appropriate refresh rate. Many systems can use the existing temperature sensor used for battery charging.
The second improvement implements a partial array refresh. This feature lets the system disable refresh to portions of the memory that are not required for normal system operation. For example, when streaming video is displayed, the entire DRAM might be refreshed because of the increased memory requirements implementing this memory intensive feature. During sleep operation, the handset can disable refresh to a large portion of the device, thus dramatically reducing power consumption. This feature requires an intelligent operating system that understands the memory requirements at any point in time.
These new DRAM devices split the power supplies, allowing further reduction in power consumption. The split supply allows the memory core to operate at one voltage while the I/O pins operate from a separate source. The supply for the I/O pins can be reduced to 1.8V, the standard for low-power memory.
DRAM in an SRAM Wrapper
Many processors developed for the wireless marketplace do not implement the newer synchronous memory bus architectures. These processors will continue to support the asynchronous memory bus for the next several years. A high-density RAM device with a legacy asynchronous interface is more appropriate for these processors.
Today, high volume SDRAMs begin at the 64 Mb density with the market quickly transitioning to the 128 Mb and 256 Mb devices. On the other end of the spectrum, asynchronous SRAM devices only reach the 8Mb density in significant volumes. 16 Mb SRAM devices are prohibitively expensive for many applications. There is a significant gap at the 16 Mb and 32 Mb densities that can be filled with a cost effective SRAM product.
Several manufacturers are offering Pseudo SRAM devices that implement the legacy asynchronous architecture, but use DRAM technology for the internal memory array. The DRAM memory cell (1 transistor, 1 capacitor) is much smaller than the standard SRAM cell (6 transistors) (see Figure 4). The smaller DRAM cell makes possible a much more cost-effective memory device than can be manufactured using SRAM technology.
In virtually every way a Pseudo SRAM operates identically to the traditional asynchronous SRAM. The required DRAM refresh operation is incorporated on-chip and is completely transparent to the host processor. Access times and Icc ACTIVE currents are comparable to standard SRAM devices. The one caveat is that the internal REFRESH operation significantly increases standby power consumption when compared to traditional SRAM. In many applications the increased standby current level is an acceptable design concession offset by the lower prices made possible by using DRAM technology.
With the functionality offered in next generation handsets, DRAM manufacturers are developing products to meet the needs of the wireless marketplace. Memory density requirements have increased and DRAM technology often provides a more cost-effective solution. At the 16 Mb and 32 Mb density levels DRAM devices are available to support the legacy asynchronous interface. Synchronous interfaces are becoming increasingly common and will probably dominate in the near future. Independent memory busses will be an increasingly popular means to provide support for high-speed synchronous memories.
The memory marketplace is becoming increasingly fragmented as different embedded applications develop unique requirements for their memory subsystems. If memory companies are to compete in this arena they must target their process technology and device architecture to meet the specific needs of the embedded developer. In the near future there will be a complete portfolio of embedded memory products evolving independently from the traditional memory marketplace.