Voice and data communication systems rely on highly accurate data converter and clocking systems to acquire, convert and manage high-speed digital and analog signals. The level of timing accuracy directly determines the data transmitting capacity of these systems. Clocking and data converter accuracy typically are measured in terms of the clock jitter or phase noise
A primary contributor to clock jitter and phase noise comes from the power systems supplying the clocking and data conversion components. As a result, very low-noise power supplies are needed. System engineers working in this area approach this challenge in multiple ways. This article gives an overview of these communication power supply challenges. Commonly used solutions are presented along with benefits and shortfalls. Also provided are detailed system performance benefits for high bandwidth low-noise LDOs, and challenges when implemented as part of the power supply.
The most important aspect of any communication system is its ability to transfer large amounts of data quickly. This is measured by the system’s data capacity and determined by the fidelity of the system’s data signals. Shannon’s Equation 1 provides a straight forward relationship between a data channel capacity and the system’s signal-to-noise ratio (SNR):
C = B x log2 (1 + SNR) Equation 1
where C is the channel capacity in bits-per-second, and B is the total system bandwidth. To have the highest channel capacity possible in a data communication system, the system designer must pay careful attention to system noise – particularly noise generated by the power supply.
Noise effects on data converter performance
A primary performance parameter of digital-to-analog converters (DACs) and analog-to-digital converters (ADCs) used in communication systems is the device’s acquisition jitter. Jitter is measured in the time domain and is defined as the variation in time of the desired clocking timing. Ideally, the inherent jitter due to thermal, flicker, shot or other noise sources in the converter is sufficiently small. This allows the converter to achieve the overall performance expected by the converters effective number of bits (ENOB).
For a 14-bit converter with a 14-bit ENOB, the ideal SNR is 86 dB as shown in Equation 2:
(SNR dB = 6.02 x n + 1.761) Equation 2
In reality, these converters are clocked by external clocking devices and powered by real power supplies. Clocking devices and power supplies are sources of jitter and can cause the data converter to perform far below its specification. If the power supply introduces only a few hundred femtoseconds of jitter, your 14-bit, high-speed ADC may only deliver 12-bit performance in your system. For example, the same 14-bit converter with 86 dB of ideal performance only has a SNR of 74.5 dB, if its jitter is degraded to 300 femtoseconds.
A simple relationship exists between the overall peak-to-peak jitter ( p-p) in the sampling of the converter and the resulting SNR performance achieved in Equation 3:
where MAX is the highest input frequency input into the converter. As shown in Equation 3, this SNR performance directly affects the overall communication system capacity. Graphically the performance looks like the graph in Figure 1.
Figure 1: SNR verses input signal frequency.
Figure 1 depicts how a 14-bit converter sampling a 100 MHz signal needs an overall jitter value of better than 0.1 ps. This allows the system designer to achieve the ideal 86 dB SNR performance and meet the targeted data capacity.
Noise effects on clocking system performance
Unlike data converters in communications systems, clocking device performance is measured using phase fluctuations. These fluctuations may be deterministic, which often are referred to as spurious noise. This noise appears as a spike in the spectral noise plot. A good example is the noise generated by the fundamental switching frequency of a DC/DC converter. The phase fluctuations also may be random which, in this case, are called phase noise. Phase noise is measured in the frequency domain like spurious noise. As with jitter in data converters, the sources of internal phase noise in clocking devices are typically thermal, flicker, or shot noise generated by the components used inside the clocking circuit.
Phase noise and non-deterministic jitter are simply different views of the same thing: undesired time domain variation in the sampled data system. There is a straight forward relationship between phase noise and random jitter. Figure 2 shows a typical phase noise plot.
Figure 2: Typical phase noise plot for a clocking device.
Note that for any area under the curve L(f) from frequency 1 to frequency 2, we can calculate a root mean square (rms) value of the phase error (?rms) equal to the results in Equation 4:
From the rms value of the phase error we can calculate the rms value of jitter by using Equation 5:
This relationship allows us to easily move between phase noise and jitter as we look at the effects of power supply noise on clocks and converters.
Power supplies as a source of jitter and phase noise
Both data converters and clocking devices are affected by power supply noise. Data converters typically have 40 to 60 dB of power supply rejection ratio (PSRR) at the frequencies on interest. For clocks, however, the effects of power supply noise are more dramatic because of their much lower PSRR, which usually is less than 20 dB. Phase noise and jitter can be introduced into the clocking and data converter systems through power supply noise. Figure 3 illustrates one method where this occurs.
Figure 3: Logic transient sensitivity to power supply noise.
A CMOS digital circuit’s logic threshold depends on the power supply voltage level, which usually is near half the power supply voltage (Figure 3). If there is noise on the power supply, the logic switch level in the device moves with the supply. This causes variation in the device timing. This variation can show up as jitter in a data converter or phase noise in a clocking system. Additionally, the power supply can inject noise into data converters and clocks sub-circuits, for example, the voltage reference and the phase-locked loop (PLL). This makes providing a low-noise power supply important to the overall system performance.
A very common power supply configuration is used in communications systems. This configuration consists of a switching regulator, followed by a filter, an LDO, then another filter (Figure 4).
Figure 4: Common power supply configuration for communication systems.
Let’s assume the system requires a low-noise 3.0V power rail for the clock or data converter. Often these systems have a main power rail of 12V. The DC/DC provides high efficiency in converting the 12V down to an intermediate rail just above the desired low-noise power rail of 4.0V, for example. Then the LDO converts the 4.0V to a low-noise 3.0V. This gives the LDO enough voltage headroom of 1V to operate with high PSRR. With lower VIN to VOUT voltages, the LDO’s PSRR degrades because of the internal amplifier’s inability to drive the power device gate.
Powering RF clock synthesizers
Let’s turn our attention to a practical application and examine the performance characteristic of a clocking device, in this case a frequency synthesizer, powered by various power sources. In our example, we chose the TRF3765 for the clocking device because it integrates a PLL and VCO and is used in high-speed communication systems. Figure 5 shows the configuration used in the measurements. The input supply for the clocking device can be switched between a switching regulator with an LDO or a lab power supply. Again, for our example, we used the TPS54320 for the switching regulator because it operates at 480 kHz and is used in communication systems. Now we are ready to examine the effects of the LDO performance on the resulting phase noise of the clocking device.
Figure 5: Block diagram of the configuration used to measure phase noise sensitivity to power supply noise.
An LDO acts as a filter between the switching regulator and the load, and often is the last stage in a power supply design. The main purpose of the LDO is to provide better voltage regulation and lower noise to the load. Often in a high-speed communication system additional filtering is used to compensate for the LDO’s shortcomings. System performance is affected by two important LDO parameters: noise and PSRR. By choosing the right LDO, system jitter and phase noise can be kept low. Also important is that the LDO can eliminate the need to filter and minimize the application’s power supply footprint.
Figure 6 highlights the importance of power supply fidelity in a high-speed communication system. Also illustrated is the clocking device’s phase noise performance with two different power supply sources. The blue line represents the clocking device’s phase noise when powered by a low noise clean lab supply as show in Figure 5. The red line represents the clocking device’s phase noise when powered by an LDO with very poor performance. The difference between the two lines illustrates that by correctly selecting the right LDO, the phase noise can be brought much closer to the ideal lab supply performance.
Figure 6: Phase noise with good and poor power supply.
PSRR as a switching noise (ripple) filter
Figure 7 represents the switching regulator’s noise output. For comparative purposes, a low-noise LDO is used. At low frequencies, the switching regulator has about ten times more noise than the LDO. At higher frequencies greater than 100 kHz, the plot shows the switching regulator’s fundamental switching frequency of 480 kHz, and the switching harmonics.
Figure 7: Switching regulator noise spectral density.
In Figure 5, the LDO conducts switching noise to the clocking device. How much noise the LDO conducts from its input to its output is determined by the LDO’s PSRR. LDO PSRR works as an active filter to attenuate the input ripple as shown in Equation 6:
PSRR is frequency-dependant and is expressed as a graph in Figure 8. The X axis show frequency and the Y axis shows PSRR in dB. The LDO shows the ideal PSRR at the fundamental switching regulator frequency of 480 kHz and for higher frequencies.
Figure 8: PSRR vs. frequency for various LDOs.
Figure 9 illustrates a phase-noise plot around 1.5 MHz frequency, which is the third harmonic of the switcher’s switching frequency. In Figure 8 the blue line represents a device with the best PSRR performance and shows the lowest peak spurious noise at 1.5 MHz. The purple line represents an LDO with poor PSRR and shows a sharp minimum peak at 1.5 MHz. The LDO with a much higher PSRR at a 1.5 MHz will reject the upstream switching nose much better. This is demonstrated by the phase noise performance of the clocking device when powered by these two devices shown in Figure 9.
Figure 9: Phase noise at the third harmonic of switching noise.
LDO internal noise
The block diagram in Figure 5 also shows that the LDO’s internal or self-generated noise contributes to the output noise. Figure 7 shows LDO devices with much lower noise than switching regulators. However, LDOs generate noise by themselves, which can degrade the performance of the devices being powered
When a switching regulator is used to power the LDO’s input, it is the LDO’s PSRR that attenuates the low-frequency noise from the switching regulator and suppresses the spikes from switching ripple. Figure 10 contains two plots. One is the LDO output noise when powered by a switching regulator. The other is the output noise when powered by a clean lab supply. The line representing a switcher and LDO combined is just the result of: 1) filtering done by the PSRR of the LDO in Figure 8, 2) of the output noise spectrum of the switching regulator in Figure 7, and 3) the addition of LDO internally generated noise. The two lines are almost identical except where the blue line shifts up slightly to show higher phase noise at frequencies around 10 kHz. This means that LDO PSRR can suppress switching regulator low-frequency noise, except around 10 KHz where the switching regulator’s noise is high enough that the LDO PSRR is insufficient to completely attenuate the switching regulator noise.
Figure 10: LDO noise with and without a switching requlator.
Figure 11 shows the noise spectral density for selected LDOs being powered by the switching regulator. The LDOs have varying low frequency noise levels. At the 480 KHz primary switching frequency of the switching regulator, the LDOs have different levels of noise spikes which correlate to their varying levels of PSRR.
Figure 11: LDO noise-powered by a switching regulator.
Figure 12 pulls it all together where we can see the clocking device’s phase noise when powered by a variety of LDOs and the switching regulator. The frequency range of 1 to 100 KHz shows the noise band caused by the LDOs internal noise. A good LDO keeps the phase noise flat in this range. By comparing Figure 11 to Figure 12, it is clear that the LDO’s noise density has direct correlation to the clock generator’s phase noise. This confirms that better noise performance in an LDO directly translates to better phase noise for clocking applications.
Figure 12: Phase noise with various LDO.
Also clear is the third harmonic of the switching regulator at 1.5 MHz, which is attenuated differently by the selected LDOs. Using different LDOs shows different capabilities to attenuate the switching regulator’s high frequency noise.
Low noise, high PSRR LDOs can make a big difference in the phase noise of a clocking device. Pay close attention to both the LDO’s internal noise as well as the PSRR performance over frequency. This ensures that you are selecting the best device to power your clocking devices and data converters. Otherwise, you may not get the performance from your data converter or clocking device that you anticipated.
- “Communication in the Presence of Noise,” Shannon, Claude E. s.l. : IEEE, 1998. PROCEEDINGS OF THE IEEE, VOL. 86, NO. 2, FEBRUARY 1998.
- “A Glossary of Analog-to-Digital Specifications and Performance Characteristics,” Application Report (SBAA147B), Baker, Bonnie, Texas Instruments, October 2011
- “Clock jitter analyzed in the time domain, Part 1,” Neu, Thomas. Analog Applications Journal, 3Q 2010, Texas Instruments, 2010.
- For more information about LDOs from Texas Instruments, visit: www.ti.com/ldo-ca
- For more information about clocking devices from Texas Instruments, visit: www.ti.com/clocks-ca.
About the Authors
Gregory Waterfall is the quiet power manager for Texas Instruments Power Management group where he is responsible for advanced product definition and development, and strategic business development. Greg received his BSEE from University of California, Berkeley, and his MBA from the University of Arizona, Tucson. If you have any questions about this article, you can contact Greg at firstname.lastname@example.org.
Masashi Nogawa is a systems and strategic marketing engineer for Texas Instruments’ Power Management group where he is responsible for networking and telecommunication LDO products. Masashi received his BSEE and MSEE degrees from the University of Electro-communications, Tokyo.
Dheepan Shanmugasundaram is a product engineer with Texas Instruments where he is responsible for precision analog product optimization. Dheepan received his BSEE from Anna University, India, and his MSEE from University of Arizona, Tucson.
Posted by Ron M. Seidel, Editorial Intern
April 18, 2012