A constant-on-time control scheme provides a simple way to implement wide-input voltage step-down converters.
Constant-on-time (COT) regulators provide transient performance with minimum design effort and component count without the requirement of loop compensation. The adaptive on-time provides immediate input voltage feed-forward and fixed switching frequency, making COTs suitable for many low power and bias applications for industrial, automotive, and telecommunications infrastructure systems.
Constant-On-Time Buck Converter
COT is a simple closed-loop control scheme for step-down (buck) converters. The block diagram and operating waveforms of a constant-on-time buck converter are shown in Figure 1. A simple COT consists of a feedback comparator and an on-timer.
When the feedback node voltage (VFB) falls below the reference voltage (t = t0, t2), the high-side buck switch is turned on and remains on for the on-timer duration. The high-side switch turns off when the on-timer expires (t = t1, t5), and does not turn on until the feedback voltage falls below the reference voltage again. In this way, the feedback voltage, and therefore the output, is regulated close to the target value.
The on-time (TON) is terminated by the on-timer, and the off-time (TOFF) is terminated by the feedback comparator. Constant-on-time converters are simple to design and have excellent line and load transient response. The absence of loop compensation makes the design easy to reuse, and makes the buck design easy to re-configure as an inverting buck-boost or isolated buck (fly-buck1).
A buck converter operating in continuous conduction mode (CCM) has the following relationship between the operating frequency (fSW) and TON:
ƒsw = D / TON = VOUT / VIN x TON (1)
An adaptive COT scheme uses this relationship by making the on-time inversely proportional to the input voltage (VIN):
TON = K RON / VIN (2)
The result is a fixed switching frequency given by:
ƒsw = VOUT / K x RON (3)
RON is the on-time programming resistor and K is proportionality constant. For a constant-on-time converter operating in CCM, the operating frequency can be programmed using the resistor RON, and is constant for a given output voltage (VOUT). The LM50082 evaluation module (EVM) is an example of a quasi-constant switching frequency (Figure 2). If the converter enters discontinuous conduction mode (DCM) at light load, then the operating frequency decreases and becomes load dependent, which lowers switching losses and increases efficiency. For converters that always remain in CCM, the operating frequency remains fairly constant, even at light load.
Constant-on-time converters require a certain amount of ripple at the feedback node (FB) to switch consistently. To ensure stability, VFB must fall monotonically during the off-time in-phase with the inductor current. Furthermore, the change in feedback voltage (∆VFB) during the off-time must be large enough to overcome any noise present at the FB and the hysteresis of the feedback comparator.
In many applications, the ripple at the FB is derived from the output voltage ripple. The nature of the output voltage ripple can be divided in two components:
∆VOUT = VESR + VC = ∆IL∙ESR + ∆IL / 8∙ƒSW∙COUT (4)
The addition is a complex summation because the resistive ripple (VESR) and the capacitive ripple (VC) are out-of-phase (Figure 3). As the VC lags the inductor current, it does not fall monotonically during the off-time. The VESR is in-phase with the inductor current and falls monotonically during the off-time. For the converter to switch consistently, the resistive component of the ripple must exceed the capacitive ripple component during the off-time:
VESR > VC (5)
In addition to the relative values of ripple at the FB, the ripple magnitude itself is important. If it is too small, it will be insufficient to trip the feedback comparator. This also results in an unstable switching pattern. In practice, a peak-to-peak ripple amplitude of 25 mV is recommended at the feedback comparator input:
∆VFB ≥ 25 mV (6)
Figure 4 shows the behavior of a constant-on-time buck converter with and without sufficient resistance in series with the output capacitor.
Rippled Generation Schemes
Type I Ripple Circuit
Using a resistance in series with the output capacitor (as shown in Figure 5) is the easiest method of ensuring ripple at the FB. The ripple is generated at the output node as the inductor ripple current flows through the series resistor, and then it is coupled to the FB by the feedback resistor divider.
The disadvantage of the above ripple generation scheme is that to generate a given amount of ripple (∆VFB) at the FB, the ripple at the output must be higher by a factor equal to the feedback resistor divider ratio. For the circuit shown in Figure 5, the output voltage ripple is four times the feedback node ripple.
Type II Ripple Circuit
For applications requiring lower output voltage ripple, the output voltage ripple can be AC-coupled to the FB using a small capacitor (Figure 6). In this case the ripple at the feedback and output nodes are similar. The required ripple resistor magnitude has also decreased accordingly.
Type III Ripple Circuit
In some applications, the power supply designer does not have complete control over the output filter capacitor network. One example is when the DC-DC converter3 in consideration has a load with input bypass capacitors. The extra capacitors suppress the ripple at the output node (Figure 7). Another example is when the output ripple requirements are very stringent because the load is sensitive to noise. For applications where is it not practical or acceptable to add a series resistor, the inductor current ripple can be emulated and injected directly at the FB (Figure 8) using an external ripple injection circuit.
The operation of the external ripple injection circuit is explained in Figure 9. The resistor Rr and the capacitor Cr form a low-pass filter that converts the rectangular SW node waveform to a triangular waveform at the ripple node (A1). The triangular waveform is then AC-coupled to the FB node by the AC-coupling capacitor CAC. The output node (VOUT) does not need to have any ripple present in this configuration, which allows independent optimization of the output filter network to meet the load ripple and transient requirements unconstrained by converter stability concerns.
Table 1 summarizes three ripple schemes along with working equations to calculate the ripple component values.
Stability & Line Regulation Trade-Off
The ripple at the FB affects the line regulation. For the three ripple schemes described in the previous section, the actual output voltage is slightly higher than the set point decided by the feedback resistor divider, because only the valley of the FB is regulated to the reference voltage (VREF) (Figure 10). The resulting average feedback voltage is higher than the target VREF by half the peak-to-peak ripple at the FB:
VFB(avg) = VREF + ∆VFB / 2 (7)
This results in a proportionately higher output voltage:
VOUT(avg) = VFB(avg) ∙ (1+ RFB2 / RFB1) = VREF∙(1+RFB2 / RFB1) + ∆VFB / 2 ∙ (1+ RFB2 / RFB1)(8)
The regulation error at the output (VOUT) is only dependent on the ripple at the feedback node (∆VFB) and ratio (RFB2/RFB1), and not on the ripple scheme. Selecting different ripple schemes affects the ripple at the output node, but not the regulation error produced for a given ∆VFB.
The ∆VFB is not a fixed parameter. It depends on the input voltage and results in line regulation component related to the injected ripple. It is desirable to keep the injected ripple magnitude as low as possible to limit the line related variation in the output voltage.
The effect of ripple on the line regulation is shown in Figure 11. The circuit operates over an input voltage range of 20 to 75 V. The feedback resistors are calculated for a 10 V target output voltage to be RFB1=1 kΩ and RFB2=7.15 kΩ. The type III ripple network is re-used from a previous design (Rr = 46.4 kΩ). The blue curves corresponding to Rr = 46.4 kΩ shows considerable deviation from the target output voltage because of excessive ripple. Using the equations for type III ripple calculation from Table 1, it is found that a larger ripple resistor Rr = 200 kΩ can generate sufficient ripple for the input voltage range 20 to 75 V. The output voltage using the revised ripple network is also shown in Figure 11. The red curve shows that this ripple network results in less than 100 mV of line regulation error.
The LM5k series of wide-VIN COTs feature adaptive on-time which, results in nearly fixed operating frequency in CCM. The ripple requirement for stable switching behavior and the different methods of creating ripple at the FB are also presented along with the operating equations. A comparative example showed why it is important to tune the ripple amplitude to get a good balance between stability and output voltage error.
This article originally appeared in the January/February print issue. Click here to read the full issue.