Field-programmable gate arrays (FPGAs) in wideband transmit systems can be expensive. Two factors that drive up FPGA cost are requirements for high internal logic speed and high-speed serializer/deserializer (SerDes). In communications systems that transmit very wideband signals, speed cannot be avoided. However, if the system does not need to occupy a large continuous bandwidth, but rather occupy two non-continuous frequency bands, is it necessary or cost-effective to require a very wideband digital up-converter (DUC) in the FPGA to process both bands together?
Until now, to generate signals with wide frequency separation in one path, the FPGA DUC had to run fast to provide the over-sampling headroom needed to place signals with wide frequency separation into the same data stream before sending to the high-speed digital-to-analog converter (DAC). But what if the DAC had its own, separate, high-speed DUCs?
By adding a multi-band summation block in a two-complex-path interpolating DAC, two FPGA DUCs can generate two complex signals at a lower rate and keep them separate at the SerDes chip-to-chip interface. The interpolating DAC can receive two, much lower rate complex signals, interpolate and mix each independently to the desired frequency separation, then combine the data into one wideband signal inside the DAC chip for single path transmit. This lowers FPGA DUC logic rates and the speed burden on the data interface between the DUC and DAC.
The following examples compare two methods and examine the benefits of each. The primary assumption leading into these examples is that the goal is not to occupy a large continuous bandwidth. Instead, it is to separate two independent bands of information at the lowest power and cost. Both examples are achievable and based on features and capabilities of new Texas Instruments DACs (DAC38J82 and DAC38J84).
Figure 1 demonstrates the most common method, which is to use a multi-channel FPGA DUC with a wideband, combined output pattern. The multi-channel FPGA DUC is operating on two blocks of information with two DUC channels. Each FPGA DUC channel interpolates and digitally mixes the carriers to a wide frequency separation, which are summed together in the FPGA. This forces a requirement for a very high-speed interface to the interpolating DAC because most of the interpolation and mixing occurred in the FPGA.
A side-note on JESD204B is helpful in understanding the complete picture. The JEDEC JESD204B supports up to 12.5 Gbps per SerDes lane. At its heart, it uses 8b/10b encoding. Every 8-bit word is serialized to a 10-bit word, or by a factor of 10 in speed. To connect to a 16-bit DAC, a total serialization factor of 20 is needed. Therefore, a 1.23 Gsps 16-bit word (the limit of the DAC38J82 and DAC38J84) requires 24.6 Gbps of 8b/10b encoded data. Since JESD204B is only supported to 12.5 Gbps, this means using two lanes per 16-bit DAC word. The FPGA DUC is generating a complex data path (IQ), so therefore four total 12.3 Gbps lanes are required to achieve a complex 16-bit 1.23 GSPS effective parallel rate to the DAC.
Assume in this example that the DAC interpolation filters have a pass band that is 80 percent of the complex data rate. The wideband FPGA DUC output speed is 1.23 GSPS (before being serialized).
About 1 GHz of complex information bandwidth is available in the pass band of the interpolation filters (±500 MHz complex). Information bandwidth is the signal bandwidth available to be occupied by intentional spectrum coming out of the FPGA DUC and into the DAC.
While almost 1 GHz of information bandwidth is nice to have, it does not come for free. An FPGA logic speed of 1.23 GSPS and SerDes speed of 6.15 Gbps (8 lanes) or 12.3 Gbps (4 lanes) is required, which can be achieved with a multi-phase digital design. This drives up the number of gates used in the FPGA by the number of clock phases, and potentially the core logic speed requirement. Also, 12.3 Gbps SerDes is only available on the highest classes of FPGAs.
Once the complex 16-bit 1.23 Gsps data is deserialized in the DAC38J82, it is interpolated by two to 2.46 Gsps. The interpolation moves the DAC analog output aliases further out of band to ease anti-alias filter requirements. This provides approximately ±1 GHz of practical NCO tuning range in the DAC mixer. The complex mixer shifts the 1 GHz of information bandwidth as a block. It cannot separate two bands within the information bandwidth because they were already combined together in the FPGA DUC.
A different approach is proposed in Figure 2. This approach takes advantage of the two-channel, complex DUC and summation block inside the quad-channel DAC38J84. Since the DAC can interpolate by as much as 16 and run 2.5 GSPS, an FPGA DUC speed of 156.25 MSPS is chosen. At that speed, each FPGA DUC has approximately 125 MHz of complex information bandwidth available to it. This is assuming the interpolation filter pass band is 80 percent of the complex data rate.
By using only 156.25 Msps, the serialization in the JESD204B now requires fewer lanes or slower speeds. Using 12.5 Gbps is still possible, but only one lane is required versus four. More likely, to save cost, an FPGA might be chosen that easily supports 156.25 Msps logic rate and 3.125 Gbps SerDes. With two complex FPGA DUC paths, four SerDes lanes are required at 3.125 Gbps, which is commonly supported in low-cost FPGAs.
Once the data is sent to the DAC and de-serialized, it is processed in two complex paths in the DAC prior to summation. Each complex path interpolates by 16 to 2.5 GSPS, and then two independent 2.5 GSPS numerically-controlled oscillators (NCOs) are used on each complex path to shift each carrier block ±1 GHz as desired. While using ±1.25 GHz is mathematically available, ±1 GHz is more achievable in practice once analog anti-alias filtering is taken into account. After individual block frequency placement, the two complex signals are summed together and sent to one pair of DACs for transmit out a single (complex) RF path. The complex RF modulator then provides further frequency tuning of the combined carrier blocks to higher frequency.