One of the most significant technological changes that has occurred in the past decade has been the shift from parallel to serial busses for high-speed system I/O and also for chip-to-chip interconnect. Examples of this trend are:

•PCI Express for PCs, servers and increasingly in networking and communications platforms

•Serial RapidIO for wireless base stations

•Infiniband and Fibre Channel for data centers

•VITA 46.X for industrial/military

Why the transition to serial busses? They offer two key advantages relative to parallel busses:

1) Much higher MByte/pin throughput

2) Easier scalability — just add additional, independent serial lanes when higher throughput is required.

Every day, high-speed serial interfaces place new demands on reference clock performance. Some of these demands include higher overall performance and more sophisticated methods to measure/verify performance, for example, frequency domain-based measurements, such as phase noise and integrated phase jitter.

Two other technologies are pushing the performance requirements of reference clocks to very high levels, even higher than the aforementioned serial busses: 100 Gigabit Ethernet and analog-to-digital converters (ADCs) on radio frequency cards, particularly in 4G base stations using the LTE standard. These types of applications require phase jitter performance as low as 0.2 picoseconds rms, which is very stringent but necessary to provide low bit error rate (BER), error vector magnitude (EVM) and low aperture error for ADCs.

These two macro-trends for timing solutions — much higher performance requirements and also more sophisticated measurement techniques — present challenges but also great opportunities. The drive for higher performance to support higher bus bandwidth greatly decreases the likelihood of integrating the clock PLL into an ASIC, thus ensuring a long-term market for reference clock chips.

This also allows clock vendors to clearly differentiate, because exceeding minimum phase noise/phase jitter specifications translates directly into better system performance via lower bit error rates.

New standards and higher-speed busses present challenges, but also great opportunities for sophisticated, responsive and system-focused clock vendors. The performance treadmill ensures long-term viability of reference clocks (militates against integration into an ASIC) and also provides great opportunities for clear performance and feature differentiation.