Silicon Labs’ Low Jitter Clock Family
Silicon Labs (Austin, TX) has introduced its next-generation Si534x “clock-tree-on-a-chip” portfolio, which includes high-performance clock generators and highly integrated multi-PLL jitter attenuators. These single-chip, ultra-low-jitter timing devices combine clock synthesis and jitter attenuation functionality to reduce the complexity of optical networking, wireless infrastructure, broadband access/aggregation, Carrier Ethernet, test and measurement, and enterprise/data center equipment including edge routers, switches, storage, and servers. The new jitter attenuators and clock generators:
- Leverage frequency flexibility and clock-tree-on-a-chip integration.
- Provide an I2C-configurable platform with a combination of frequency translation capabilities and jitter performance of <100 fs RMS.
- Combines up to 4 independent jitter-attenuating PLLs and up to 5 ultra-low-jitter MultiSynth fractional synthesizers.
- Are capable of generating up to 10 outputs with any combination of frequencies from 100 Hz to 800 MHz in a wide range of user-selectable output formats (LVPECL, LVDS, CML, HCSL and LVCMOS).
For more information visit www.silabs.com.