ADS Controlled Impedance Line Designer
Agilent Technologies (Santa Clara, CA) introduced Agilent EEsof EDA’s Controlled Impedance Line Designer. The software product quickly and accurately optimizes stack up and line geometry for multigigabit-per-second chip-to-chip links, using the most relevant metric. Features include:
- An integrated Controlled Impedance Line Designer and existing Channel Simulator that lets engineers see a set of eye openings that result from sweeping through the pre-layout design parameters (e.g., line width).
- A cross-sectional (2D) electromagnetic field solver.
- A frequency-dependent Svensson/Djordjevic permittivity, which ensures both accuracy and delay causality.
For more information, visit www.agilent.com