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New Voltage Regulator Controller Families for AMD Processors

Mon, 09/20/2010 - 10:18am
CHiL Semiconductor Corporation announces the new M2 and Nashoba families of high efficiency computing voltage regulator (VR) controllers for Advanced Micro Devices (AMD) processor and memory solutions. The controllers provide the highest efficiency, lowest cost of ownership solution in the industry by automatically adjusting operating conditions to optimize efficiency at all currents.

The M2 product family supports Magny-Cours CPUs, as well as memory in systems built around AMD’s G34 and C32 sockets. The M2 family offers from 4 to 8 phase solutions and exceptional efficiency. As a truly digital power solution, the M2 also offers exceptional density. Its true-digital control includes a full suite of integrated overclocking and telemetry features. M2 is even backward-compatible to AM2 solutions.

The Nashoba product family provides the same high efficiency and high density solutions as M2 in a lower phase count, lower cost solution. It is ideal for AM3 desktop solutions, including the newly introduced 890GX chipset, as well as memory solutions and entry level server solutions. Enhanced security features are offered on this family.

Both families of VR controllers provide the highest efficiency, lowest cost of ownership solution in the industry by automatically adjusting operating conditions to optimize efficiency at low, medium, and high currents. Compared to analog controllers, CHiL typically saves 40 discrete components, significantly reducing board space per controller as well as decreasing electronic waste. Since the controllers contain fewer pins and components, they have double the reliability of comparable analog controllers.

The new line will go into production near the end of the first quarter of 2010. Both the new families contain CHiL’s efficiency-shaping features. In idle state, CHiL’s proprietary discontinuous-mode operation requires no sensing circuitry and can be configured digitally to minimize losses in idle and sleep states. No special driver interface is required. In low current modes, the automatic dynamic phase control optimizes the number of operating phases to minimize power losses. In systems where there are no PSI signals, such as DDR Memory, CHiL products can be tuned to reach the highest possible efficiency. When the CPU rapidly increases current, CHiL’s adaptive transient algorithm (ATA) automatically and instantly adapts by adding phases, without the need for additional decoupling.

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