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Multicore Processor Family Provides Intelligent SoC Management for Embedded Applications

Tue, 09/28/2010 - 9:34am
Applied Micro Circuits Corporation or AppliedMicro, announced its next-generation PacketPro™ multicore processor System-on-a-Chip (SoC) family, designed with advanced subsystem and offload acceleration hardware to enable new levels of security, high availability, low latency, and power management for embedded applications.

PacketPro is AppliedMicro’s second-generation embedded processor SoC family and the first to feature offload of critical features for multiple PowerPC® processors with frequency capabilities ranging in performance from 600 MHz to 2.0 GHz and beyond. The innovative SoC subsystem design features the Scalable Lightweight Intelligent Management processor or SLIMpro™ to enable breakthrough flexibility in SoC power management, protected asymmetric multiprocessing (PMP), failover protection, resiliency and end-to-end security for a wide range of mission-critical applications in wireless and wired networking, multi-function printer, industrial, access point markets.

Each device introduced into the PacketPro family enables multiple, concurrent operating systems (OS) while providing resource protection (processors, memory and I/O) that each domain operates in a transparent, independent and protected mode. It also enables application-aware and usage-based power management to reduce energy consumption. The multi-level crypto engine offers simultaneous wire-speed performance along with investment protection against product cloning and hardware-software tampering.

AppliedMicro developed the PacketPro multicore SoC architecture specifically in response to developers’ need to manage abundant on-chip resources as the industry shifts from single core to multicore applications. These enhanced management capabilities help developers address the ongoing explosion in bandwidth, the growth of converged network applications and green energy initiatives.

PacketPro also features configurable offload engines for in-line packet processing, security, traffic classification, shaping and queue management to relieve the main processor complex.

The AppliedMicro PacketPro family features performance of up to 2 GHz per core, 32 KB L1 I/D & 256 KB dedicated L2 cache per core, support for full symmetric multiprocessing (SMP) and ultra flexible asymmetric multiprocessing (AMP). Memory and bus architecture supports 16/32/64-bit DDR2/3 up to 1,600Mbps and beyond with ECC option. Connectivity features include PCI-e Gen 2 controller, GE, 10GE, SGMII, RGMII, IEEE1588 Rev2 on all Ethernet ports, USB 2.0 – H/D, OTG, all with integrated PHY, USB 3.0, SATA ports and SDHC.

The PacketPro family is manufactured on a 40nm TSMC® CMOS process and is available in both wire-bond and flip-chip packaging.

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