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Advanced FPGA Workflow and Design Optimizations in Simulink HDL Coder 2.0

Tue, 09/14/2010 - 11:19am
MathWorks announces a major update to Simulink HDL Coder which adds critical path analysis and area-speed optimizations for automatic HDL code generation, along with a new Workflow Advistor for FPGA implementations.

Simulink HDL Coder enables a rapid FPGA prototyping workflow and generates synthesizable Verilog and VHDL code from Simulink models, MATLAB code, and Stateflow charts. The generated HDL code can be simulated and synthesized using industry-standard tools for FPGA and ASIC implementation and verification.

Features and Benefits include:

•Generation of target-independent, synthesizable HDL code from Simulink models, MATLAB code, and Stateflow charts

•Support for data path and control logic designs, including finite-state machines and more than 160 IP blocks for math, signal processing, and communications

•FPGA Workflow Advisor to automate code generation and FPGA implementation process

•Generation of RTL test benches and cosimulation models

•Resource sharing and retiming options for area-speed tradeoffs

•Simulink model optimization using timing-constraint information and HDL synthesis tools

•Code-to-model and model-to-code traceability for DO-254

•Legacy code integration.

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