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Power Optimization Product Leverages Sequential Analysis Technology to Deliver Complete RTL Power Optimization Solution

Tue, 01/26/2010 - 8:07am
SANTA CLARA, Calif. -- Calypto® Design Systems Inc. recently announced a new PowerAdviser Flow that enables designers to deliver one of the most power-optimized SoC designs possible. Using sequential design information generated by Calypto's PowerPro CG and PowerPro MG tools, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power. The award-winning PowerPro product family is used by SoC designers for networking, computer, consumer, and wireless applications.

"Our goal is to provide SoC designers with the most comprehensive RTL power optimization platform available, enabling the creation of devices with the lowest power consumption possible despite increasing design complexity,"said Tom Sandoval, chief executive officer of Calypto Design Systems.

"With our PowerAdviser Flow, designers now have the capability to easily achieve their power goals through either automated or manual RTL optimization."

Identification of RTL modifications for power savings can represent up to 50 percent of the total manual power optimization effort. The PowerAdviser Flow automates the process of thoroughly investigating power optimization opportunities in an RTL design using the visualization capability provided by Calypto's® PowerPro Analyzer tool. Designers can therefore more quickly understand where to invest design time for power reduction.

The PowerAdviser Flow presents design optimizations in the form of RTL changes, schematics, and textual descriptions. Quantifiable power savings for every potential optimization is provided in the form of a hyperlinked table.

The PowerAdviser Flow is available in the PowerPro 3.1 release. In addition to the PowerAdviser Flow, the PowerPro 3.1 release includes new features and capabilities to reduce power in logic, registers, clocks, and embedded memories, including new sequential optimization techniques to reduce dynamic and leakage memory power, ECO support, and 64-bit support for optimizing larger designs.

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