Analyzer Speeds Assertion and Design Debug by up to 10X
Thu, 10/08/2009 - 12:09pm
OneSpin Solutions, provider of 360 MV, a comprehensive formal assertion-based verification (ABV) solution, recently announced its new RootCauseAnalyzer that boosts formal ABV productivity by making SystemVerilog assertion (SVA) and RTL design debug much easier and faster. An integral part of OneSpin's 360 MV solution, the RootCauseAnalyzer provides some of the most advanced debug automation capabilities available in formal ABV tools today. It eliminates most of the time-consuming, error-prone manual analysis of complex information otherwise necessary to trace the root causes of assertion failures, speeding assertion and design debug by up to 10x. RootCauseAnalyzer consists of four tightly integrated debug components. These constitute a unique debug flow that automates the tracing of assertion failures back to their root cause incorrect assertion code, missing constraints, or a bug in the RTL source code.