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30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes

Thu, 10/29/2009 - 11:22am
MOUNTAIN VIEW, Calif., /PRNewswire-FirstCall/ -- Synopsys, Inc. today announced the addition of the new DesignWare® USB 2.0 picoPHY IP to its USB 2.0 PHY IP product line that has been successfully deployed in more than 300 customer designs, and in more than 50 different process technologies ranging from 180-nanometer (nm) to 32-nm.

Targeted at mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices and netbooks, the DesignWare USB 2.0 picoPHY supports advanced 28-nm processes in a 1.8V architecture, is 30 percent smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption.

The DesignWare USB 2.0 picoPHY IP is the first PHY IP to support the new Battery Charging version 1.1 and USB On-the-Go (OTG) version 2.0 specifications from the USB Implementer's Forum (USB-IF). The Battery Charging v 1.1 specification allows mobile devices to draw up to 1.8 A of current when connected to a wall charger.

The Battery Charging specification enables portable devices to distinguish among various power sources, such as a wall charger, standard host port and USB charging port, and selects the most efficient method to charge the device.

By supporting the USB OTG version 2.0 specification, the DesignWare USB 2.0 picoPHY incorporates the new Attached Detection Protocol (ADP) feature, which improves the power efficiency of portable devices that communicate directly to USB peripherals without the need for a PC Host.

In addition the DesignWare USB 2.0 picoPHY supports advanced power management features, such as power supply gating and support for ultra-low standby current to help designers lower the leakage power of mobile system-on-chips (SoCs) while maintaining the integrity of the USB 2.0 connection.

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