Automated Tool Enables SoC Designers to Produce the Lowest Power Memory Implementation Possible
Mon, 08/03/2009 - 9:13am
Enabling a breakthrough in automated system on a chip (SoC) design, Calypto® Design Systems Inc. announces the availability of its PowerPro MG (memory gating) tool. The new tool is believed to be the first product that automatically generates power-optimized RTL by taking advantage of the low-power modes available in today’s leading on-chip memories. Employing a new “memory gating” technique, PowerPro MG eliminates costly and time-consuming manual coding. By automatically generating logic to control low-power modes, PowerPro MG enables the lowest-power SoC possible and reduces that portion of the design cycle from weeks to hours. Using the company’s patented sequential analysis technology, the tool constructs new memory gating logic that works in conjunction with the low-power memory modes to produce the lowest power memory implementation possible.