Diagnosis Technology Slashes Debug Effort for Complex SystemVerilog Assertions
Wed, 02/25/2009 - 10:46am
OneSpin Solutions has mainstreamed comprehensive formal assertion-based verification (ABV) for SoC, ASIC and FPGA designs by delivering a structured, step-by-step approach to its use and adoption. This approach is enabled by five interoperable products in a new, integrated 360® MV product family designed for formal verification novices, experienced users, and experts. Entry and exit points at six application levels let companies best meet their verification needs. OneSpin also announced a new proof-based debugger for complex SystemVerilog Assertions (SVAs). The debugger automatically locates the root-cause that makes an assertion fail, addressing a critical productivity issue in the use of complex assertions. It complements simulation-based verification and requires up to 5X less verification effort than thorough module/subsystem testbenches.