CPLDs Serve Handheld Designs
Tue, 12/30/2008 - 7:21am
Lattice Semiconductor’s ispMACH 4064ZE and ispMACH 4128ZE CPLDs (complex programmable logic devices) target high-volume, handheld designs. The 6 × 6-mm devices exhibit typ. standby current of 10 µA, a nominal 1.8-V power supply with operation down to 1.6 V, Power Guard dynamic power reduction, per pin pull-up, pull-down or bus keeper control; input hysteresis and an on-chip user oscillator and timer. The components’ 5-V tolerant I/O connect to TTL and PCI interfaces with no external components for connecting to legacy chips and interfaces. The CPLDs offer 2 I/O banks, each with its own power supply voltage that can be set at the appropriate level to support LVTTL and LVCMOS 3.3-, 2.5-, 1.8- and 1.5-V outputs, and input buffers with programmable thresholds supporting the above standards independent of the I/O bank voltage.