Advertisement
Product Releases
Advertisement

What are the critical technical challenges of 3-D ICs? And how will this technology impact the semiconductor food chain?

Thu, 10/09/2008 - 6:03am
Welcome to Brainstorm!

Kathy Cook, 3-D Business Development, SUSS Microtec

Semiconductor ICs face constant pressure for increased performance while still decreasing their size. At the same time, their packages must be able to accommodate to new functionalities. 3-D IC is the most ‘integrated’ packaging approach. However, strong technical challenges need to be overcome, such as chip thermal management, industrial wafer-to-wafer bonding tools, low-cost through-wafer structures and via filling processes, among others.

In order to continually increase IC performance while decreasing the size, 3-D IC device makers must be able to increase the I/O density. Smaller diameter through silicon vias allow for a smaller TSV pitch distance. With the availability of smaller diameter vias, the requirement for wafer bonder alignment accuracy will move to the submicron range for post-bond alignment. Precision alignment is needed to allow sufficient overlap of the TSV contact areas for good electrical connections with low resistance.

As a leading supplier of wafer bonding equipment, one of the key challenges for SUSS is to understand our customers’ roadmaps for 3-D ICs, and to translate those plans into equipment requirements. Before the introduction of 3-D integration, wafer bonders were used mainly for MEMS applications where cap wafers were bonded to the MEMS device wafers. Alignment accuracy requirements weren’t nearly as stringent for MEMS as they are for 3-D ICs.

There are several different types of bonds involved in 3-D integration. Device manufacturers can use metal diffusion, fusion or adhesive bonds to stack the layers together. Each type of bond has different advantages and disadvantages, and each type requires different wafer conditions prior to bonding. As a wafer bonder supplier to the 3-D IC market, SUSS must understand these different requirements and be able to offer solutions to every customer. In many 3-D IC process sequences, there is a step where one of the wafers must be thinned and handled during its thinned state. Often a temporary handle wafer is attached to the wafer prior to thinning so that the wafer will not warp or crack after it is thinned. The attachment of the handle wafer involves bonding — usually a direct bond or an adhesive bond. The requirements for this type of bond are different from those of a permanent bond, so a new wafer bonder platform has been developed that is optimized for this process.

Of course, understanding the timing for these requirements is critical. One issue that we often see is that customers want capabilities for their equipment now that may never be practical in a manufacturing environment due to high cost per wafer processed. It is essential for us as equipment manufacturers to track our customers’ roadmap in order to have the equipment and process capabilities ready when the market requires these capabilities.

Lee Smith, Amkor Technology

3-D ICs are foremost an architectural choice with Through Silicon Vias (TSV) as an interconnect technology that presents design and fabrication challenges across the supply chain. The first challenge is properly timing the introduction of a 3-D IC component to ensure that the performance benefits from this new 3-D architecture will outweigh the added development and manufacturing costs for the target application. The second challenge is ensuring that there is a design integration team approach with expertise across the supply chain from IC architecture, fabrication, package assembly and final test to ensure the design is optimized for cost and performance requirements based on the supply chain’s capabilities.

The team needs experience, thorough capability/reliability data, armed with a methodology to make the complex trade-off decisions for TSV interconnects from design rules through process materials and manufacturing flow. TSV supply chains and process options can be complex, so risks must be understood and mitigation plans should be exercised to test the limits of the process technology and supply chain.

At this stage, there are no standards in place for the interconnection and stacking of different IC devices to form a 3-D IC architecture. Thus, integrating heterogeneous devices, such as logic with memory or digital with analog, will require very close collaboration between the design teams or IC suppliers to develop a 3-D IC component. The scope of this collaboration must go beyond the design and technical aspects to encompass the business and logistic considerations. Lessons learned from heterogeneous integration using 3-D packaging technology indicates that the business and logistic models may be enabled or constrained by the technology selected.

Advertisement

Share this Story

X
You may login with either your assigned username or your e-mail address.
The password field is case sensitive.
Loading