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How can today’s FPGAs enable designers to deliver high performance while at the same time reduce systems costs, board space and component count?

Mon, 09/08/2008 - 6:45am

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OEMs need to design products that are not only scalable and cost-effective, but also flexible and reusable across multiple evolving standards.
"Reinvented" Programmable Solutions ?Are Essential For Next-Generation ?Wireless Deployment
Shakeel Peera, Director of Strategic Marketing, Lattice Semiconductor Corporation
Wireless TEMs (Telecom Equipment Manufacturers) are under pressure to deploy basestation architectures that have smaller footprints, consume less power and cost less to build, deploy and operate. This pressure is juxtaposed with the need to improve flexibility, coverage, bandwidth and scalability while rolling out new services through mobile WiMax and LTE networks.

A key strategy in achieving this is the use of programmable logic, which today combines the traditional benefits of programmability with integrated "hard" features like high-speed parallel DSP capabilities to enable the implementation of RF and Baseband processing functionality. Lately, emerging serial interconnect standards (e.g. CPRI/OBSAI) have enabled TEMs to mix and match modules from partner manufacturers and to deploy multiple, remotely distributed antenna arrays for increased coverage and capacity, all with reduced footprints, operational costs and power consumption. Within the processing circuitry itself, designers are using FPGAs as DSP co-processors, and this requires yet another type of serial interconnect such as Serial Rapid I/O. Finally, as all-IP networks become the norm, Ethernet connectivity will be essential. Consequently FPGAs must integrate high-speed memory, DSP and multi-protocol serial interconnect.

Historically, such features have been the exclusive domain of expensive, high performance, high power FPGAs, which limited their use to mere prototyping vehicles. Alternatively, traditional, bare bones low-cost FPGAs have lacked the necessary features. What has been needed is a radical paradigm shift that marries a low cost/power FPGA fabric to high speed processing and interconnect elements. One such "reinvented" FPGA is the LatticeECP2M, and I expect more of these new classes of FPGAs to emerge to satisfy the needs of the wireless market.
Customizable MCUs Help Achieve both Cost and Power Consumption Targets
Jay Johnson, Marketing Director, Atmel Corporation
FPGAs are a great vehicle for prototyping and emulation — proving your digital design does what it was spec'd to do, and concurrently developing software applications. However, when it comes to power and cost, real engineers know that migrating the FPGA code and committing the design to silicon can make the difference in a successful product and a market failure. BOM cost and power consumption are the biggest drivers for many consumer wireless markets.

In order to achieve target BOM and power consumption targets, Atmel offers its AT91CAP customizable microcontroller – a single chip, standard product microcontroller, with a metal programmable (MP) block that is used to implement the FPGA portion of the design. By predefining the most common features in a microcontroller and then leaving a little bit of silicon for personalization, we address the standards evolution issue. For a nominal NRE, AT91CAP MCUs deliver 8x better performance, consume 98% less static power and cost about 30% less than FPGAs.

The CAP-DK Development Kit has an emulation board with an ARM-based MCU and FPGA that can be used to co-design the RTL and C-code. This design can then be deployed using Atmel’s CAP7E MCU and a discrete FPGA. The RTL code from this design can be ported directly to the MP block on the AT91CAP MCU. Designers get the flexibility they need and also can meet their power consumption and performance targets. Atmel will turn the design from final gate level net list to prototypes in less than 3 months.
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