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OEM Mixed Language Simulator for FPGA Design

Mon, 06/16/2008 - 10:52am

Lattice Semiconductor Corporation announces an agreement that will deliver an OEM FPGA mixed language simulator. Active-HDL Lattice Edition will be bundled with the ispLEVER design tool suite, providing mixed language simulation (VHDL, Verilog and SystemVerilog), co-simulation with Simulink from The MathWorks and simulation support for Lattice encrypted IP Cores. It provides high performance simulation for Lattice designs, mixed HDL language support and productivity enhancers ranging from testbench generation from a graphical waveform to co-simulation with The MathWorks Simulink. The Web Edition is designed for single language simulation, either VHDL or Verilog, and smaller designs more typical of devices supported by the ispLEVER Starter and ispLEVER Classic tools. The simulator provides support for all Lattice CPLD/FPGA devices. ?
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