FPGA Increases Verification Productivity
Tue, 01/22/2008 - 5:53am
OneSpin Solutions GmbH announces its stand-alone 360 EC-FPGA sequential equivalence checker that is dedicated to the FPGA market. It supports all sequential optimizations performed by FPGA synthesis tools, enabling designers to verify functionality without disabling the advanced synthesis optimizations vital to achieving functional and performance goals. Support includes all Altera Stratix and Cyclone FPGAs, HardCopy, most Xilinx Spartan and Virtex products, and the Synplicity Synplify Pro synthesis flow, including gated clock conversion. Synthesis tool independent, the FPGA verifies functional equivalence between the register transfer level (RTL) code and post-synthesis FPGA netlist, and between the post-synthesis netlist and post-place-and-route FPGA netlist. It supports both prototyping and production-part verification.